qorvo PAC55XX 2024.04.27 ARM Cortex-M4 processor with FPU, running up to 150MHz with a set of analog and digital peripherals for power and motor control applications. CM4 r0p1 little true true 3 true 8 32 ADC 2.5 MSPS, 12-bit SAR ADC ADC 0x0 0x0 0x10000 registers n ADC0 ADC 0 Interrupt 3 ADC1 ADC 1 Interrupt 4 ADC2 ADC 2 Interrupt 5 ADC3 ADC 3 Interrupt 6 ADCCTL ADC Control 0x8 read-write n 0x0 0x0 ADCINT ADC Interrupt Control 0x10 read-write n 0x0 0x0 ADCRES ADC Result 0xC read-write n 0x0 0x0 DTSERES0 DTSE Result 0 0x200 read-write n 0x0 0x0 DTSERES1 DTSE Result 1 0x204 read-write n 0x0 0x0 DTSERES10 DTSE Result 10 0x228 read-write n 0x0 0x0 DTSERES11 DTSE Result 11 0x22C read-write n 0x0 0x0 DTSERES12 DTSE Result 12 0x230 read-write n 0x0 0x0 DTSERES13 DTSE Result 13 0x234 read-write n 0x0 0x0 DTSERES14 DTSE Result 14 0x238 read-write n 0x0 0x0 DTSERES15 DTSE Result 15 0x23C read-write n 0x0 0x0 DTSERES16 DTSE Result 16 0x240 read-write n 0x0 0x0 DTSERES17 DTSE Result 17 0x244 read-write n 0x0 0x0 DTSERES18 DTSE Result 18 0x248 read-write n 0x0 0x0 DTSERES19 DTSE Result 19 0x24C read-write n 0x0 0x0 DTSERES2 DTSE Result 2 0x208 read-write n 0x0 0x0 DTSERES20 DTSE Result 20 0x250 read-write n 0x0 0x0 DTSERES21 DTSE Result 21 0x254 read-write n 0x0 0x0 DTSERES22 DTSE Result 22 0x258 read-write n 0x0 0x0 DTSERES23 DTSE Result 23 0x25C read-write n 0x0 0x0 DTSERES3 DTSE Result 3 0x20C read-write n 0x0 0x0 DTSERES4 DTSE Result 4 0x210 read-write n 0x0 0x0 DTSERES5 DTSE Result 5 0x214 read-write n 0x0 0x0 DTSERES6 DTSE Result 6 0x218 read-write n 0x0 0x0 DTSERES7 DTSE Result 7 0x21C read-write n 0x0 0x0 DTSERES8 DTSE Result 8 0x220 read-write n 0x0 0x0 DTSERES9 DTSE Result 9 0x224 read-write n 0x0 0x0 DTSESEQCFG0 DTSE Sequence Config 0 0x80 read-write n 0x0 0x0 DTSESEQCFG1 DTSE Sequence Config 1 0x84 read-write n 0x0 0x0 DTSESEQCFG10 DTSE Sequence Config 10 0x108 read-write n 0x0 0x0 DTSESEQCFG11 DTSE Sequence Config 11 0x10C read-write n 0x0 0x0 DTSESEQCFG12 DTSE Sequence Config 12 0x110 read-write n 0x0 0x0 DTSESEQCFG13 DTSE Sequence Config 13 0x114 read-write n 0x0 0x0 DTSESEQCFG14 DTSE Sequence Config 14 0x118 read-write n 0x0 0x0 DTSESEQCFG15 DTSE Sequence Config 15 0x11C read-write n 0x0 0x0 DTSESEQCFG16 DTSE Sequence Config 16 0x120 read-write n 0x0 0x0 DTSESEQCFG17 DTSE Sequence Config 17 0x124 read-write n 0x0 0x0 DTSESEQCFG18 DTSE Sequence Config 18 0x128 read-write n 0x0 0x0 DTSESEQCFG19 DTSE Sequence Config 19 0x12C read-write n 0x0 0x0 DTSESEQCFG2 DTSE Sequence Config 2 0x88 read-write n 0x0 0x0 DTSESEQCFG20 DTSE Sequence Config 20 0x130 read-write n 0x0 0x0 DTSESEQCFG21 DTSE Sequence Config 21 0x134 read-write n 0x0 0x0 DTSESEQCFG22 DTSE Sequence Config 22 0x138 read-write n 0x0 0x0 DTSESEQCFG23 DTSE Sequence Config 23 0x13C read-write n 0x0 0x0 DTSESEQCFG3 DTSE Sequence Config 3 0x8C read-write n 0x0 0x0 DTSESEQCFG4 DTSE Sequence Config 4 0x90 read-write n 0x0 0x0 DTSESEQCFG5 DTSE Sequence Config 5 0x94 read-write n 0x0 0x0 DTSESEQCFG6 DTSE Sequence Config 6 0x98 read-write n 0x0 0x0 DTSESEQCFG7 DTSE Sequence Config 7 0x9C read-write n 0x0 0x0 DTSESEQCFG8 DTSE Sequence Config 8 0x100 read-write n 0x0 0x0 DTSESEQCFG9 DTSE Sequence Config 9 0x104 read-write n 0x0 0x0 DTSETRIGENT0TO3 DTSE Trigger Entry 0 to 3 0x40 read-write n 0x0 0x0 DTSETRIGENT12TO15 DTSE Trigger Entry 12 to 15 0x4C read-write n 0x0 0x0 DTSETRIGENT16TO19 DTSE Trigger Entry 16 to 19 0x50 read-write n 0x0 0x0 DTSETRIGENT20TO23 DTSE Trigger Entry 20 to 23 0x54 read-write n 0x0 0x0 DTSETRIGENT24TO27 DTSE Trigger Entry 24 to 27 0x58 read-write n 0x0 0x0 DTSETRIGENT28TO31 DTSE Trigger Entry 28 to 31 0x5C read-write n 0x0 0x0 DTSETRIGENT4TO7 DTSE Trigger Entry 4 to 7 0x44 read-write n 0x0 0x0 DTSETRIGENT8TO11 DTSE Trigger Entry 8 to 11 0x48 read-write n 0x0 0x0 EMUXCTL EMUX Control 0x0 read-write n 0x0 0x0 EMUXDATA EMUX Data 0x4 read-write n 0x0 0x0 CAN CAN Peripheral CAN 0x0 0x0 0x10000 registers n CAN CAN Interrupt 27 ACR Combined CAN Acceptance Code registers 0x10 read-write n 0x0 0x0 ACR0 CAN Acceptance Code 0 0 7 ACR1 CAN Acceptance Code 1 8 7 ACR2 CAN Acceptance Code 2 16 7 ACR3 CAN Acceptance Code 3 24 7 ALC_TXERR_RXERR_ECC Combined CAN ECC, RXERR, TXERR, and ALC registers 0x18 read-write n 0x0 0x0 ALC CAN Arbitration Lost Code Capture 24 7 ECC CAN Error Code Capture 0 7 RXERR CAN RX Error Counter 8 7 TXERR CAN TX Error Counter 16 7 AMR Combined CAN Acceptance Mask registers 0x14 read-write n 0x0 0x0 AMR0 CAN Acceptance Mask 0 0 7 AMR1 CAN Acceptance Mask 1 8 7 AMR2 CAN Acceptance Mask 2 16 7 AMR3 CAN Acceptance Mask 3 24 7 BTR1_BTR0_RMC_IMR Combined CAN IMR, RMC, BTR0, and BTR1 registers 0x4 read-write n 0x0 0x0 BTR0 CAN Bus Timing Register 0 16 7 BTR1 CAN Bus Timing Register 1 24 7 IMR CAN Interrupt Mask 0 7 RMC CAN Receive Message Counter 8 7 ISR_SR_CMR_MR Combined CAN MR, CMR, SR, and ISR registers 0x0 read-write n 0x0 0x0 CMR CAN Command 8 7 ISR CAN Interrupt Status/Acknowledge 24 7 MR CAN Mode 0 7 SR CAN Status 16 7 RXBUF Combined CAN Receive Buffer registers 0xC read-write n 0x0 0x0 RXBUF0 CAN Receive Buffer 0 0 7 RXBUF1 CAN Receive Buffer 1 8 7 RXBUF2 CAN Receive Buffer 2 16 7 RXBUF3 CAN Receive Buffer 3 24 7 TXBUF Combined CAN Transmit Buffer registers 0x8 read-write n 0x0 0x0 TXBUF0 CAN Transmit Buffer 0 0 7 TXBUF1 CAN Transmit Buffer 1 8 7 TXBUF2 CAN Transmit Buffer 2 16 7 TXBUF3 CAN Transmit Buffer 3 24 7 CRC CRC Module CRC 0x0 0x0 0x400 registers n CTL CRC Control 0x0 read-write n 0x0 0x0 DATAIN CRC Data Input 0x4 read-write n 0x0 0x0 DATAOUT CRC Data Output 0xC read-write n 0x0 0x0 SEED CRC Seed Value 0x8 read-write n 0x0 0x0 GPIOA GPIO A GPIOA 0x0 0x0 0x400 registers n GPIOA GPIOA Interrupt 15 DEBOUNCE GPIO A De-bounce Filter 0x2C read-write n 0x0 0x0 DOCLEAR GPIO A Data Output Clear 0x34 read-write n 0x0 0x0 DOSET GPIO A Data Output Set 0x30 read-write n 0x0 0x0 IN GPIO A Data Input Value 0xC read-write n 0x0 0x0 INTCLEAR GPIO A Interrupt Clear 0x1C read-write n 0x0 0x0 INTEDGEBOTH GPIO A Interrupt Edge Both 0x28 read-write n 0x0 0x0 INTEN GPIO A Interrupt Enable 0x10 read-write n 0x0 0x0 INTFLAGMASKED GPIO A Interrupt Flag Masked 0x18 read-write n 0x0 0x0 INTFLAGRAW GPIO A Interrupt Flag Raw 0x14 read-write n 0x0 0x0 INTTYPE GPIO A Interrupt Type 0x20 read-write n 0x0 0x0 INTVALUE GPIO A Interrupt Value 0x24 read-write n 0x0 0x0 MODE GPIO A Pin Mode Select 0x0 read-write n 0x0 0x0 OUT GPIO A Data Output Value 0x8 read-write n 0x0 0x0 OUTMASK GPIO A Data Output Write Mask 0x4 read-write n 0x0 0x0 GPIOB GPIO B GPIOB 0x0 0x0 0x400 registers n GPIOB GPIO B Interrupt 16 DEBOUNCE GPIO B De-bounce Filter 0x2C read-write n 0x0 0x0 DOCLEAR GPIO B Data Output Clear 0x34 read-write n 0x0 0x0 DOSET GPIO B Data Output Set 0x30 read-write n 0x0 0x0 IN GPIO B Data Input Value 0xC read-write n 0x0 0x0 INTCLEAR GPIO B Interrupt Clear 0x1C read-write n 0x0 0x0 INTEDGEBOTH GPIO B Interrupt Edge Both 0x28 read-write n 0x0 0x0 INTEN GPIO B Interrupt Enable 0x10 read-write n 0x0 0x0 INTFLAGMASKED GPIO B Interrupt Flag Masked 0x18 read-write n 0x0 0x0 INTFLAGRAW GPIO B Interrupt Flag Raw 0x14 read-write n 0x0 0x0 INTTYPE GPIO B Interrupt Type 0x20 read-write n 0x0 0x0 INTVALUE GPIO B Interrupt Value 0x24 read-write n 0x0 0x0 MODE GPIO B Pin Mode Select 0x0 read-write n 0x0 0x0 OUT GPIO B Data Output Value 0x8 read-write n 0x0 0x0 OUTMASK GPIO B Data Output Write Mask 0x4 read-write n 0x0 0x0 GPIOC GPIO C GPIOC 0x0 0x0 0x400 registers n GPIOC GPIO C Interrupt 17 DEBOUNCE GPIO C De-bounce Filter 0x2C read-write n 0x0 0x0 DOCLEAR GPIO C Data Output Clear 0x34 read-write n 0x0 0x0 DOSET GPIO C Data Output Set 0x30 read-write n 0x0 0x0 IN GPIO C Data Input Value 0xC read-write n 0x0 0x0 INTCLEAR GPIO C Interrupt Clear 0x1C read-write n 0x0 0x0 INTEDGEBOTH GPIO C Interrupt Edge Both 0x28 read-write n 0x0 0x0 INTEN GPIO C Interrupt Enable 0x10 read-write n 0x0 0x0 INTFLAGMASKED GPIO C Interrupt Flag Masked 0x18 read-write n 0x0 0x0 INTFLAGRAW GPIO C Interrupt Flag Raw 0x14 read-write n 0x0 0x0 INTTYPE GPIO C Interrupt Type 0x20 read-write n 0x0 0x0 INTVALUE GPIO C Interrupt Value 0x24 read-write n 0x0 0x0 MODE GPIO C Pin Mode Select 0x0 read-write n 0x0 0x0 OUT GPIO C Data Output Value 0x8 read-write n 0x0 0x0 OUTMASK GPIO C Data Output Write Mask 0x4 read-write n 0x0 0x0 GPIOD GPIO D GPIOD 0x0 0x0 0x400 registers n GPIOD GPIO D Interrupt 18 DEBOUNCE GPIO D De-bounce Filter 0x2C read-write n 0x0 0x0 DOCLEAR GPIO D Data Output Clear 0x34 read-write n 0x0 0x0 DOSET GPIO D Data Output Set 0x30 read-write n 0x0 0x0 IN GPIO D Data Input Value 0xC read-write n 0x0 0x0 INTCLEAR GPIO D Interrupt Clear 0x1C read-write n 0x0 0x0 INTEDGEBOTH GPIO D Interrupt Edge Both 0x28 read-write n 0x0 0x0 INTEN GPIO D Interrupt Enable 0x10 read-write n 0x0 0x0 INTFLAGMASKED GPIO D Interrupt Flag Masked 0x18 read-write n 0x0 0x0 INTFLAGRAW GPIO D Interrupt Flag Raw 0x14 read-write n 0x0 0x0 INTTYPE GPIO D Interrupt Type 0x20 read-write n 0x0 0x0 INTVALUE GPIO D Interrupt Value 0x24 read-write n 0x0 0x0 MODE GPIO D Pin Mode Select 0x0 read-write n 0x0 0x0 OUT GPIO D Data Output Value 0x8 read-write n 0x0 0x0 OUTMASK GPIO D Data Output Write Mask 0x4 read-write n 0x0 0x0 GPIOE GPIO E GPIOE 0x0 0x0 0x400 registers n GPIOE GPIO E Interrupt 19 DEBOUNCE GPIO E De-bounce Filter 0x2C read-write n 0x0 0x0 DOCLEAR GPIO E Data Output Clear 0x34 read-write n 0x0 0x0 DOSET GPIO E Data Output Set 0x30 read-write n 0x0 0x0 IN GPIO E Data Input Value 0xC read-write n 0x0 0x0 INTCLEAR GPIO E Interrupt Clear 0x1C read-write n 0x0 0x0 INTEDGEBOTH GPIO E Interrupt Edge Both 0x28 read-write n 0x0 0x0 INTEN GPIO E Interrupt Enable 0x10 read-write n 0x0 0x0 INTFLAGMASKED GPIO E Interrupt Flag Masked 0x18 read-write n 0x0 0x0 INTFLAGRAW GPIO E Interrupt Flag Raw 0x14 read-write n 0x0 0x0 INTTYPE GPIO E Interrupt Type 0x20 read-write n 0x0 0x0 INTVALUE GPIO E Interrupt Value 0x24 read-write n 0x0 0x0 MODE GPIO E Pin Mode Select 0x0 read-write n 0x0 0x0 OUT GPIO E Data Output Value 0x8 read-write n 0x0 0x0 OUTMASK GPIO E Data Output Write Mask 0x4 read-write n 0x0 0x0 GPIOF GPIO F GPIOF 0x0 0x0 0x400 registers n GPIOF GPIO F Interrupt 20 DEBOUNCE GPIO F De-bounce Filter 0x2C read-write n 0x0 0x0 DOCLEAR GPIO F Data Output Clear 0x34 read-write n 0x0 0x0 DOSET GPIO F Data Output Set 0x30 read-write n 0x0 0x0 IN GPIO F Data Input Value 0xC read-write n 0x0 0x0 INTCLEAR GPIO F Interrupt Clear 0x1C read-write n 0x0 0x0 INTEDGEBOTH GPIO F Interrupt Edge Both 0x28 read-write n 0x0 0x0 INTEN GPIO F Interrupt Enable 0x10 read-write n 0x0 0x0 INTFLAGMASKED GPIO F Interrupt Flag Masked 0x18 read-write n 0x0 0x0 INTFLAGRAW GPIO F Interrupt Flag Raw 0x14 read-write n 0x0 0x0 INTTYPE GPIO F Interrupt Type 0x20 read-write n 0x0 0x0 INTVALUE GPIO F Interrupt Value 0x24 read-write n 0x0 0x0 MODE GPIO F Pin Mode Select 0x0 read-write n 0x0 0x0 OUT GPIO F Data Output Value 0x8 read-write n 0x0 0x0 OUTMASK GPIO F Data Output Write Mask 0x4 read-write n 0x0 0x0 GPIOG GPIO G GPIOG 0x0 0x0 0x400 registers n GPIOG GPIO G Interrupt 21 DEBOUNCE GPIO G De-bounce Filter 0x2C read-write n 0x0 0x0 DOCLEAR GPIO G Data Output Clear 0x34 read-write n 0x0 0x0 DOSET GPIO G Data Output Set 0x30 read-write n 0x0 0x0 IN GPIO G Data Input Value 0xC read-write n 0x0 0x0 INTCLEAR GPIO G Interrupt Clear 0x1C read-write n 0x0 0x0 INTEDGEBOTH GPIO G Interrupt Edge Both 0x28 read-write n 0x0 0x0 INTEN GPIO G Interrupt Enable 0x10 read-write n 0x0 0x0 INTFLAGMASKED GPIO G Interrupt Flag Masked 0x18 read-write n 0x0 0x0 INTFLAGRAW GPIO G Interrupt Flag Raw 0x14 read-write n 0x0 0x0 INTTYPE GPIO G Interrupt Type 0x20 read-write n 0x0 0x0 INTVALUE GPIO G Interrupt Value 0x24 read-write n 0x0 0x0 MODE GPIO G Pin Mode Select 0x0 read-write n 0x0 0x0 OUT GPIO G Data Output Value 0x8 read-write n 0x0 0x0 OUTMASK GPIO G Data Output Write Mask 0x4 read-write n 0x0 0x0 GPTIMERA General Purpose Timer A (GPTimer A) GPTIMERA 0x0 0x0 0x10000 registers n GPTIMERA GPTimer A Interrupt 28 CTL GPTimer A Control 0x0 read-write n 0x0 0x0 CTR GPTimer A Counter 0x4 read-write n 0x0 0x0 GPTIMERB General Purpose Timer B (GPTimer B) GPTIMERB 0x0 0x0 0x10000 registers n GPTIMERB GPTimer B Interrupt 29 CTL GPTimer B Control 0x0 read-write n 0x0 0x0 CTR GPTimer B Counter 0x4 read-write n 0x0 0x0 I2C I2C Peripheral I2C 0x0 0x0 0x10000 registers n I2C I2C Interrupt 22 ADR0 I2C Slave Address 0 0x14 read-write n 0x0 0x0 ADR1 I2C Slave Address 1 0x28 read-write n 0x0 0x0 ADR2 I2C Slave Address 2 0x30 read-write n 0x0 0x0 ADR3 I2C Slave Address 3 0x38 read-write n 0x0 0x0 ADRM0 I2C Slave Address Mask 0 0x18 read-write n 0x0 0x0 ADRM1 I2C Slave Address Mask 1 0x2C read-write n 0x0 0x0 ADRM2 I2C Slave Address Mask 2 0x34 read-write n 0x0 0x0 ADRM3 I2C Slave Address Mask 3 0x3C read-write n 0x0 0x0 CLK I2C Clock Control 0x10 read-write n 0x0 0x0 CONCLR I2C Control Clear 0x4 read-write n 0x0 0x0 CONSET I2C Control Set 0x0 read-write n 0x0 0x0 DAT I2C Data 0xC read-write n 0x0 0x0 RST I2C Software Reset 0x24 read-write n 0x0 0x0 STAT I2C Status 0x8 read-write n 0x0 0x0 XADR0 I2C Extended Slave Address 0 0x1C read-write n 0x0 0x0 XADRM0 I2C Extended Slave Address Mask 0 0x20 read-write n 0x0 0x0 MEMCTL Memory Controller MEMCTL 0x0 0x0 0x400 registers n 0x0 0x400 registers n MEMCTL MEMCTL Interrupt 0 FLASHERASE FLASH Erase 0x20 read-write n 0x0 0x0 FLASHLOCK FLASH Lock Access 0x8 read-write n 0x0 0x0 FLASHPAGE FLASH Page 0xC read-write n 0x0 0x0 MEMCTL Memory Controller Configuration 0x0 32 read-write n 0x0 0x0 CACHEDIS FLASH Read Cache Disable 21 22 read-write Enabled FLASH Read Cache Enabled 0 Disabled FLASH Read Cache Disabled 1 DEIE ECC Dual bit Error Interrupt Enable 17 18 read-write Disabled ECC Dual bit Error Interrupt Disabled 0 Enabled ECC Dual bit Error Interrupt Enabled 1 ECCDIS SRAM ECC Disable 20 21 read-write Enabled SRAM ECC Enabled 0 Disabled SRAM ECC Disabled 1 INVADDRIE Invalid Memory Address Access Interrupt Enable 18 19 read-write Disabled Invalid Memory Interrupt Disabled 0 Enabled Invalid Memory Interrupt Enabled 1 MCLKDIV MCLK Divider 4 8 read-write HCLK /1 MCLK 0 HCLK /2 MCLK 1 HCLK /11 MCLK 10 HCLK /12 MCLK 11 HCLK /13 MCLK 12 HCLK /14 MCLK 13 HCLK /15 MCLK 14 HCLK /16 MCLK 15 HCLK /3 MCLK 2 HCLK /4 MCLK 3 HCLK /5 MCLK 4 HCLK /6 MCLK 5 HCLK /7 MCLK 6 HCLK /8 MCLK 7 HCLK /9 MCLK 8 HCLK /10 MCLK 9 MCLKSEL MCLK Mux Select 22 23 read-write ROSCCLK ROSC Clock selected as input to MCLK 0 MCLK HCLK / MCLKDIV 1 SEIE ECC Single bit Error Interrupt Enable 16 17 read-write Disabled ECC Single bit Error Interrupt Disabled 0 Enabled ECC Single bit Error Interrupt Enabled 1 STDBY FLASH Standby Mode 19 20 read-write Normal Normal Mode 0 Standby Standby Mode 1 WRITEWORDCNT Write Word Data Count 8 10 read-write WSTATE FLASH Access Wait States 0 4 read-write 0 WS 0 Wait States 0 1 WS 1 Wait State 1 10 WS 10 Wait States 10 11 WS 11 Wait States 11 12 WS 12 Wait States 12 13 WS 13 Wait States 13 14 WS 14 Wait States 14 15 WS 15 Wait States 15 2 WS 2 Wait States 2 3 WS 3 Wait States 3 4 WS 4 Wait States 4 5 WS 5 Wait States 5 6 WS 6 Wait States 6 7 WS 7 Wait States 7 8 WS 8 Wait States 8 9 WS 9 Wait States 9 MEMSTATUS Memory Controller Status 0x4 32 read-write n 0x0 0x0 DE ECC Dual bit Error Detection Flag 17 18 read-write No Flag No ECC Dual bit Error Flag 0 Flag ECC Dual bit Error Flag Set 1 EBUSY FLASH Erase Busy 1 2 read-write Not Busy FLASH erase operation not in progress 0 Busy FLASH erase operation in progress 1 INVADDR Invalid Memory Address Access Flag 18 19 read-write No Flag No Invalid Memory Flag 0 Flag Invalid Memory Flag Set 1 SE ECC Single bit Error Detection Flag 16 17 read-write No FLag No ECC Single bit Error Flag 0 Flag ECC Single bit Error Flag Set 1 WBUSY FLASH Write Busy 0 1 read-write Not Busy FLASH write operation not in progress 0 Busy FLASH write operation in progress 1 WRITEWORDCNT Write Word Data Count 8 10 read-write SWDUNLOCK SWD Unlock 0x10 read-write n 0x0 0x0 RTC Real-Time Clock (RTC) with Calendar RTC 0x0 0x0 0x400 registers n RTC RTC Interrupt 2 ALARMSET RTC Alarm Setting 0x14 read-write n 0x0 0x0 CTL RTC Control 0x0 read-write n 0x0 0x0 DATE RTC Date 0x8 read-write n 0x0 0x0 DATESET RTC Date Setting 0x10 read-write n 0x0 0x0 TIME RTC Time 0x4 read-write n 0x0 0x0 TIMESET RTC Time Setting 0xC read-write n 0x0 0x0 SCC System and Clock Control SCC 0x0 0x0 0x400 registers n SCC SCC Interrupt 30 CCSCTL DESC 0x0 32 read-write n 0x0 0x0 ACLKDIV ACLK Divider 20 23 read-write SCLK /1 ACLK 0 SCLK /2 ACLK 1 SCLK /3 ACLK 2 SCLK /4 ACLK 3 SCLK /5 ACLK 4 SCLK /6 ACLK 5 SCLK /7 ACLK 6 SCLK /8 ACLK 7 ACLKEN ACLK Enable 13 14 read-write Disabled ACLK Disabled 0 Enabled ACLK Enabled 1 ADCLKEN ADCCLK Enable 14 15 read-write Disabled ADCCLK Disabled 0 Enabled ADCCLK Enabled 1 CLKFAILEN Clock Fail Enable 5 6 read-write Disabled Clock Fail Disabled 0 Enabled Clock Fail Enabled 1 CLKFAILIF Clock Fail Interrupt Flag 7 8 read-write Not Set Int Flag Not Set 0 Set Int Flag Set 1 CLKFAILMUXSEL Clock Fail Mux Select 6 7 read-write FRCLK FRCLK selected as input to Clock Fail 0 PLLCLK PLLCLK selected as input to Clock Fail 1 FRCLKMUXSEL FRCLK MUX Select 0 2 read-write ROSC ROSC selected as input to FRCLK 0 CLKREF CLKREF selected as input to FRCLK 1 Reserved1 Reserved1 Description 2 EXTCLK External Clock selected as input to FRCLK 3 HCLKDIV HCLK Divider 24 27 read-write SCLK /1 HCLK 0 SCLK /2 HCLK 1 SCLK /3 HCLK 2 SCLK /4 HCLK 3 SCLK /5 HCLK 4 SCLK /6 HCLK 5 SCLK /7 HCLK 6 SCLK /8 HCLK 7 LDOEN 1.8V LDO Enable 8 9 read-write Disabled 1.8V LDO Disabled 0 Enabled 1.8V LDO Enabled 1 PCLKDIV PCLK Divider 16 19 read-write HCLK /1 PCLK 0 HCLK /2 PCLK 1 HCLK /3 PCLK 2 HCLK /4 PCLK 3 HCLK /5 PCLK 4 HCLK /6 PCLK 5 HCLK /7 PCLK 6 HCLK /8 PCLK 7 PCLKEN PCLK Enable 12 13 read-write Disabled PCLK Disabled 0 Enabled PCLK Enabled 1 ROSCEN ROSC Enable 2 3 read-write Disabled ROSC Disabled 0 Enabled ROSC Enabled 1 SCLKMUXSEL SCLK Mux Select 4 5 read-write FRCLK FRCLK selected as input to SCLK 0 PLLCLK PLLCLK selected as input to SCLK 1 STCLKSLPEN SysTick Clock Sleep Enable 15 16 read-write Disabled SysTick clock active in deep sleep 0 Enabled SysTick clock gated in deep sleep 1 SWRESET Software Reset 11 12 read-write Not Reset SW Reset Not Initiated 0 Reset SW Reset Initiated 1 USAMODE USART A Mode 28 29 read-write SSP SSP Mode 0 UART UART Mode 1 USBMODE USART B Mode 29 30 read-write SSP SSP Mode 0 UART UART Mode 1 USCMODE USART C Mode 30 31 read-write SSP SSP Mode 0 UART UART Mode 1 USDMODE USART D Mode 31 32 read-write SSP SSP Mode 0 UART UART Mode 1 CCSPLLCTL DESC 0x4 read-write n 0x0 0x0 PLLBP PLL Bypass 1 2 read-write Inactive PLL is not bypassed 0 Active PLL is bypassed 1 PLLEN PLL Enable 0 1 read-write Disabled PLL Disabled 0 Enabled PLL Enabled 1 PLLFBDIV PLL Feedback Divider 8 22 read-write PLLINDIV PLL Input Divider 4 8 read-write PLLLOCK PLL Lock Status 24 25 read-write Not Locked PLL is not locked 0 Locked PLL is locked 1 PLLOUTDIV PLL Output Divider 2 4 read-write /1 PLL output divided by 1 0 /2 PLL output divided by 2 1 /3 PLL output divided by 3 2 /4 PLL output divided by 4 3 CCSROSCTRIM DESC 0x8 read-write n 0x0 0x0 PADS PA Drive Strength/Schmitt Trigger 0x60 read-write n 0x0 0x0 PAMUXSEL PA Peripheral MUX Select 0xC 32 read-write n 0x0 0x0 PA0 PA0 MUX Select 0 3 read-write GPIOA0 GPIO selected 0 PA1 PA1 MUX Select 4 7 read-write GPIOA1 GPIO selected 0 EMUXD EMUX Data Selected 1 PA2 PA2 MUX Select 8 11 read-write GPIOA2 GPIO selected 0 EMUXC EMUX Clock Selected 1 PA3 PA3 MUX Select 12 15 read-write GPIOA3 GPIO selected 0 USASCLK USART A SCLK Selected 1 USBSCLK USART B SCLK Selected 2 PA4 PA4 MUX Select 16 19 read-write GPIOA4 GPIO selected 0 USAMOSI USART A MOSI/TX Selected 1 USBMOSI USART B MOSI/TX Selected 2 PA5 PA5 MUX Select 20 23 read-write GPIOA5 GPIO selected 0 USAMISO USART A MISO/RX Selected 1 USBMISO USART B MISO/RX Selected 2 PA6 PA6 MUX Select 24 27 read-write GPIOA6 GPIO selected 0 USASS USART A SPI Slave Select 1 USBSS USART B SPI Slave Select 2 PA7 PA7 MUX Select 28 31 read-write GPIOA7 GPIO selected 0 PAPDEN PA Weak Pull-down Enable 0x44 read-write n 0x0 0x0 PAPUEN PA Weak Pull-up Enable 0x28 read-write n 0x0 0x0 PBDS PB Drive Strength/Schmitt Trigger 0x64 read-write n 0x0 0x0 PBMUXSEL PB Peripheral MUX Select 0x10 32 read-write n 0x0 0x0 PB0 PB0 MUX Select 0 3 read-write GPIOB0 GPIO selected 0 TAPWM0 Timer A PWM0 Selected 1 TBPWM0 Timer B PWM0 Selected 2 TCPWM0 Timer C PWM0 Selected 4 TDPWM0 Timer D PWM0 Selected 5 PB1 PB1 MUX Select 4 7 read-write GPIOB1 GPIO selected 0 TAPWM1 Timer A PWM1 Selected 1 TBPWM1 Timer B PWM1 Selected 2 TCPWM1 Timer C PWM1 Selected 4 TDPWM1 Timer D PWM1 Selected 5 PB2 PB2 MUX Select 8 11 read-write GPIOB2 GPIO selected 0 TAPWM2 Timer A PWM2 Selected 1 TBPWM2 Timer B PWM2 Selected 2 TCPWM2 Timer C PWM2 Selected 4 TDPWM2 Timer D PWM2 Selected 5 PB3 PB3 MUX Select 12 15 read-write GPIOB3 GPIO selected 0 TAPWM3 Timer A PWM3 Selected 1 TBPWM3 Timer B PWM3 Selected 2 TCPWM3 Timer C PWM3 Selected 4 TDPWM3 Timer D PWM3 Selected 5 PB4 PB4 MUX Select 16 19 read-write GPIOB4 GPIO selected 0 TAPWM4 Timer A PWM4 Selected 1 TBPWM4 Timer B PWM4 Selected 2 TCPWM0 Timer C PWM0 Selected 3 TCPWM4 Timer C PWM4 Selected 4 TDPWM4 Timer D PWM4 Selected 5 PB5 PB5 MUX Select 20 23 read-write GPIOB5 GPIO selected 0 TAPWM5 Timer A PWM5 Selected 1 TBPWM5 Timer B PWM5 Selected 2 TCPWM1 Timer C PWM1 Selected 3 TCPWM5 Timer C PWM5 Selected 4 TDPWM5 Timer D PWM5 Selected 5 PB6 PB6 MUX Select 24 27 read-write GPIOB6 GPIO selected 0 TAPWM6 Timer A PWM6 Selected 1 TBPWM6 Timer B PWM6 Selected 2 TCPWM2 Timer C PWM2 Selected 3 TCPWM6 Timer C PWM6 Selected 4 TDPWM6 Timer D PWM6 Selected 5 PB7 PB7 MUX Select 28 31 read-write GPIOB7 GPIO selected 0 TAPWM7 Timer A PWM7 Selected 1 TBPWM7 Timer B PWM7 Selected 2 TCPWM3 Timer C PWM3 Selected 3 TCPWM7 Timer C PWM7 Selected 4 TDPWM7 Timer D PWM7 Selected 5 PBPDEN PB Weak Pull-down Enable 0x48 read-write n 0x0 0x0 PBPUEN PB Weak Pull-up Enable 0x2C read-write n 0x0 0x0 PCDS PC Drive Strength/Schmitt Trigger 0x68 read-write n 0x0 0x0 PCMUXSEL PC Peripheral MUX Select 0x14 32 read-write n 0x0 0x0 PC0 PC0 MUX Select 0 3 read-write GPIOC0 GPIO selected 0 TBPWM0 Timer B PWM0 Selected 1 TCPWM0 Timer C PWM0 Selected 2 TBQEPIDX Timer B QEP Index Selected 3 USBMOSI USART B MOSI/TX Selected 4 USCSCLK USART C SPI Clock Selected 5 CANRXD CAN Rx Data Selected 6 I2CSCL I2C SCL Selected 7 PC1 PC1 MUX Select 4 7 read-write GPIOC1 GPIO selected 0 TBPWM1 Timer B PWM1 Selected 1 TCPWM1 Timer C PWM1 Selected 2 TBQEPPHA Timer B QEP Phase A Selected 3 USBMISO USART B MISO/RX Selected 4 USCSS USART C Slave Select Selected 5 CANTXD CAN Tx Data Selected 6 I2CSDA I2C SDA Selected 7 PC2 PC2 MUX Select 8 11 read-write GPIOC2 GPIO selected 0 TBPWM2 Timer B PWM2 Selected 1 TCPWM2 Timer C PWM2 Selected 2 TBQEPPHB Timer B QEP Phase B Selected 3 USBSCLK USART B SCLK Selected 4 USCMOSI USART C MOSI/TX Selected 5 EMUXD EMUX Data Selected 7 PC3 PC3 MUX Select 12 15 read-write GPIOC3 GPIO selected 0 TBPWM3 Timer B PWM3 Selected 1 TCPWM3 Timer C PWM3 Selected 2 USBSS USART B Slave Select Selected 4 USCMISO USART C MISO/RX Selected 5 EMUXC EMUX Clock Selected 7 PC4 PC4 MUX Select 16 19 read-write GPIOC4 GPIO selected 0 TBPWM4 Timer B PWM4 Selected 1 TCPWM4 Timer C PWM4 Selected 2 TCQEPIDX Timer C QEP Index Selected 3 USBMOSI USART B MOSI/TX Selected 4 USCSCLK USART C SPI Clock Selected 5 CANRXD CAN Rx Data Selected 6 I2CSCL I2C SCL Selected 7 PC5 PC5 MUX Select 20 23 read-write GPIOC5 GPIO selected 0 TBPWM5 Timer B PWM5 Selected 1 TCPWM5 Timer C PWM5 Selected 2 TCQEPPHA Timer C QEP Phase A Selected 3 USBMISO USART B MISO/RX Selected 4 USCSS USART C Slave Select Selected 5 CANTXD CAN Tx Data Selected 6 I2CSDA I2C SDA Selected 7 PC6 PC6 MUX Select 24 27 read-write GPIOC6 GPIO selected 0 TBPWM6 Timer B PWM6 Selected 1 TCPWM6 Timer C PWM6 Selected 2 TCQEPPHB Timer C QEP Phase B Selected 3 USBSCLK USART B SCLK Selected 4 USCMOSI USART C MOSI/TX Selected 5 EMUXD EMUX Data Selected 7 PC7 PC7 MUX Select 28 31 read-write GPIOC7 GPIO selected 0 TBPWM7 Timer B PWM7 Selected 1 TCPWM7 Timer C PWM7 Selected 2 USBSS USART B Slave Select Selected 4 USCMISO USART C MISO/RX Selected 5 FRCLK FRCLK Output Selected 6 EMUXC EMUX Clock Selected 7 PCPDEN PC Weak Pull-down Enable 0x4C read-write n 0x0 0x0 PCPUEN PC Weak Pull-up Enable 0x30 read-write n 0x0 0x0 PDDS PD Drive Strength/Schmitt Trigger 0x6C read-write n 0x0 0x0 PDMUXSEL PD Peripheral MUX Select 0x18 32 read-write n 0x0 0x0 PD0 PD0 MUX Select 0 3 read-write GPIOD0 GPIO selected 0 TBPWM0 Timer B PWM0 Selected 1 TCPWM0 Timer C PWM0 Selected 2 TDQEPIDX Timer D QEP Index Selected 3 USCSCLK USART C SPI Clock Selected 5 CANTXD CAN Tx Data Selected 6 EMUXD EMUX Data Selected 7 PD1 PD1 MUX Select 4 7 read-write GPIOD1 GPIO selected 0 TBPWM1 Timer B PWM1 Selected 1 TCPWM1 Timer C PWM1 Selected 2 TDQEPPHA Timer D QEP Phase A Selected 3 USCSS USART C Slave Select Selected 5 CANRXD CAN Rx Data Selected 6 EMUXC EMUX Clock Selected 7 PD2 PD2 MUX Select 8 11 read-write GPIOD2 GPIO selected 0 TBPWM2 Timer B PWM2 Selected 1 TCPWM2 Timer C PWM2 Selected 2 TDQEPPHB Timer D QEP Phase B Selected 3 USCMOSI USART C MOSI/TX Selected 5 PD3 PD3 MUX Select 12 15 read-write GPIOD3 GPIO selected 0 TBPWM3 Timer B PWM3 Selected 1 TCPWM3 Timer C PWM3 Selected 2 USCMISO USART C MISO/RX Selected 5 FRCLK FRCLK output selected 6 TRACED3 TRACE Data 3 output selected 7 PD4 PD4 MUX Select 16 19 read-write GPIOD4 GPIO selected 0 TBPWM4 Timer B PWM4 Selected 1 TCPWM4 Timer C PWM4 Selected 2 TDQEPIDX Timer D QEP Index Selected 3 TBQEPIDX Timer B QEP Index Selected 4 USDSCLK USART D SPI Clock Selected 5 TRACED3 TRACE Data 3 output selected 6 USDMOSI USART D MOSI/TX Selected 7 PD5 PD5 MUX Select 20 23 read-write GPIOD5 GPIO selected 0 TBPWM5 Timer B PWM5 Selected 1 TCPWM5 Timer C PWM5 Selected 2 TDQEPPHA Timer D QEP Phase A Selected 3 TDQEPPHB Timer D QEP Phase B Selected 4 USDSCLK USART D SPI Clock Selected 5 CANRXD CAN Rx Data Selected 6 USDMISO USART D MISO/RX Selected 7 PD6 PD6 MUX Select 24 27 read-write GPIOD6 GPIO selected 0 TBPWM6 Timer B PWM6 Selected 1 TCPWM6 Timer C PWM6 Selected 2 TDQEPPHB Timer D QEP Phase B Selected 3 TBQEPPHB Timer B QEP Phase B Selected 4 USDMOSI USART D MOSI/TX Selected 5 CANTXD CAN Tx Data Selected 6 I2CSDA I2C SDA Selected 7 PD7 PD7 MUX Select 28 31 read-write GPIOD7 GPIO selected 0 TBPWM7 Timer B PWM7 Selected 1 TCPWM7 Timer C PWM7 Selected 2 USDMISO USART C MISO/RX Selected 5 CANRXD CAN Rx Data Selected 6 I2CSCL I2C SCL Selected 7 PDPDEN PD Weak Pull-down Enable 0x50 read-write n 0x0 0x0 PDPUEN PD Weak Pull-up Enable 0x34 read-write n 0x0 0x0 PEDS PE Drive Strength/Schmitt Trigger 0x70 read-write n 0x0 0x0 PEMUXSEL PE Peripheral MUX Select 0x1C 32 read-write n 0x0 0x0 PE0 PE0 MUX Select 0 3 read-write GPIOE0 GPIO selected 0 TCPWM4 Timer C PWM4 Selected 1 TDPWM0 Timer D PWM0 Selected 2 TAQEPIDX Timer A QEP Index Selected 3 TBQEPIDX Timer B QEP Index Selected 4 USCSCLK USART C SPI Clock Selected 5 I2CSCL I2C SCL Selected 6 EMUXC EMUX Clock Selected 7 PE1 PE1 MUX Select 4 7 read-write GPIOE1 GPIO selected 0 TCPWM5 Timer C PWM5 Selected 1 TDPWM1 Timer D PWM1 Selected 2 TAQEPPHA Timer A QEP Phase A Selected 3 TBQEPPHA Timer B QEP Phase A Selected 4 USCSS USART C Slave Select Selected 5 I2CSDA I2C SDA Selected 6 EMUXD EMUX Data Selected 7 PE2 PE2 MUX Select 8 11 read-write GPIOE2 GPIO selected 0 TCPWM6 Timer C PWM6 Selected 1 TDPWM2 Timer D PWM2 Selected 2 TAQEPPHB Timer A QEP Phase B Selected 3 TBQEPPHB Timer B QEP Phase B Selected 4 USCMOSI USART C MOSI/TX Selected 5 CANRXD CAN Rx Data Selected 6 EXTCLK External clock input Selected 7 PE3 PE3 MUX Select 12 15 read-write GPIOE3 GPIO selected 0 TCPWM7 Timer C PWM7 Selected 1 TDPWM3 Timer D PWM3 Selected 2 FRCLK FRCLK Output Selected 3 USCMISO USART C MISO/RX Selected 5 CANTXD CAN Tx Data Selected 6 PE4 PE4 MUX Select 16 19 read-write GPIOE4 GPIO selected 0 TCPWM4 Timer C PWM4 Selected 1 TDPWM4 Timer D PWM4 Selected 2 TDQEPIDX Timer D QEP Index Selected 3 USBSCLK USART B SCLK Selected 4 USDMOSI USART D MOSI/TX Selected 5 I2CSCL I2C SCL Selected 6 PE5 PE5 MUX Select 20 23 read-write GPIOE5 GPIO selected 0 TCPWM5 Timer C PWM5 Selected 1 TDPWM5 Timer D PWM5 Selected 2 TDQEPPHA Timer D QEP Phase A Selected 3 USBSS USART B Slave Select Selected 4 USDMISO USART D MISO/RX Selected 5 I2CSDA I2C SDA Selected 6 PE6 PE6 MUX Select 24 27 read-write GPIOE6 GPIO selected 0 TCPWM6 Timer C PWM6 Selected 1 TDPWM6 Timer D PWM6 Selected 2 TDQEPPHB Timer D QEP Phase B Selected 3 USBMOSI USART B MOSI/TX Selected 4 USDSCLK USART D SCLK Selected 5 CANRXD CAN RX Data Selected 6 PE7 PE7 MUX Select 28 31 read-write GPIOE7 GPIO selected 0 TCPWM7 Timer C PWM7 Selected 1 TDPWM7 Timer D PWM7 Selected 2 USBMISO USART B MISO/RX Selected 4 USDSS USART D Slave Select Selected 5 CANTXD CAN TX Data Selected 6 PEPDEN PE Weak Pull-down Enable 0x54 read-write n 0x0 0x0 PEPUEN PE Weak Pull-up Enable 0x38 read-write n 0x0 0x0 PFDS PF Drive Strength/Schmitt Trigger 0x74 read-write n 0x0 0x0 PFMUXSEL PF Peripheral MUX Select 0x20 32 read-write n 0x0 0x0 PF0 PF0 MUX Select 0 3 read-write GPIOF0 GPIO selected 0 TCPWM0 Timer C PWM0 Selected 1 TDPWM0 Timer D PWM0 Selected 2 TCK_SWDCLK TCK/SWDCLK Selected 3 TBQEPIDX Timer B QEP Index Selected 4 USBSCLK USART B SPI Clock Selected 5 TRACED2 TRACED2 Selected 6 TRACECLK TRACECLK Selected 7 PF1 PF1 MUX Select 4 7 read-write GPIOF1 GPIO selected 0 TCPWM1 Timer C PWM1 Selected 1 TDPWM1 Timer D PWM1 Selected 2 TMS_SWDIO TMS/SWDIO Selected 3 TBQEPPHA Timer B QEP Phase A Selected 4 USBSS USART B Slave Select Selected 5 TRACED1 TRACED1 Selected 6 TRACED0 TRACED0 Selected 7 PF2 PF2 MUX Select 8 11 read-write GPIOF2 GPIO selected 0 TCPWM2 Timer C PWM2 Selected 1 TDPWM2 Timer D PWM2 Selected 2 TDI TDI Selected 3 TBQEPPHB Timer B QEP Phase B Selected 4 USBMOSI USART B MOSI/TX Selected 5 TRACED0 TRACED0 Selected 6 TRACED1 TRACED1 Selected 7 PF3 PF3 MUX Select 12 15 read-write GPIOF3 GPIO selected 0 TCPWM3 Timer C PWM3 Selected 1 TDPWM3 Timer D PWM3 Selected 2 TDO TDO Selected 3 FRCLK FRCLK Output Selected 4 USBMISO USART B MISO/RX Selected 5 TRACECLK TRACECLK Selected 6 TRACED2 TRACED2 Selected 7 PF4 PF4 MUX Select 16 19 read-write GPIOF4 GPIO selected 0 TCPWM4 Timer C PWM4 Selected 1 TDPWM4 Timer D PWM4 Selected 2 TCQEPIDX Timer C QEP Index Selected 4 USDSCLK USART D SCLK Selected 5 TRACED3 TRACED3 Selected 6 EMUXC EMUX Clock Selected 7 PF5 PF5 MUX Select 20 23 read-write GPIOF5 GPIO selected 0 TCPWM5 Timer C PWM5 Selected 1 TDPWM5 Timer D PWM5 Selected 2 TCQEPPHA Timer C QEP Phase A Selected 4 USDSS USART D Slave Select Selected 5 EMUXD EMUX Data Selected 7 PF6 PF6 MUX Select 24 27 read-write GPIOF6 GPIO selected 0 TCPWM6 Timer C PWM6 Selected 1 TDPWM6 Timer D PWM6 Selected 2 TCQEPPHB Timer C QEP Phase B Selected 4 USDMOSI USART D MOSI/TX Selected 5 CANRXD CAN RX Data Selected 6 I2CSCL I2C SCL Selected 7 PF7 PF7 MUX Select 28 31 read-write GPIOF7 GPIO selected 0 TCPWM7 Timer C PWM7 Selected 1 TDPWM7 Timer D PWM7 Selected 2 USDMISO USART D MISO/RX Selected 5 CANTXD CAN TX Data Selected 6 I2CSDA I2C SDA Selected 7 PFPDEN PF Weak Pull-down Enable 0x58 read-write n 0x0 0x0 PFPUEN PF Weak Pull-up Enable 0x3C read-write n 0x0 0x0 PGDS PG Drive Strength/Schmitt Trigger 0x78 read-write n 0x0 0x0 PGMUXSEL PG Peripheral MUX Select 0x24 32 read-write n 0x0 0x0 PG0 PG0 MUX Select 0 3 read-write GPIOG0 GPIO selected 0 TCPWM0 Timer C PWM0 Selected 1 TDPWM0 Timer D PWM0 Selected 2 EMUXC EMUX Clock Selected 3 USDSCLK USART D SPI Clock Selected 5 TRACECLK TRACECLK Selected 6 TCQEPIDX Timer C QEP Index Selected 7 PG1 PG1 MUX Select 4 7 read-write GPIOG1 GPIO selected 0 TCPWM1 Timer C PWM1 Selected 1 TDPWM1 Timer D PWM1 Selected 2 EMUXD EMUX Data Selected 3 USDSS USART D Slave Select Selected 5 TRACED0 TRACED0 Selected 6 TCQEPPHA Timer C QEP Phase A Selected 7 PG2 PG2 MUX Select 8 11 read-write GPIOG2 GPIO selected 0 TCPWM2 Timer C PWM2 Selected 1 TDPWM2 Timer D PWM2 Selected 2 FRCLK FRCLK Output Selected 3 USDMOSI USART D MOSI/TX Selected 5 TRACED1 TRACED1 Selected 6 TCQEPPHB Timer C QEP Phase B Selected 7 PG3 PG3 MUX Select 12 15 read-write GPIOG3 GPIO selected 0 TCPWM3 Timer C PWM3 Selected 1 TDPWM3 Timer D PWM3 Selected 2 USDMISO USART D MISO/RX Selected 5 TRACED2 TRACED2 Selected 6 PG4 PG4 MUX Select 16 19 read-write GPIOG4 GPIO selected 0 TCPWM4 Timer C PWM4 Selected 1 TDPWM4 Timer D PWM4 Selected 2 EMUXD EMUX Data Selected 3 I2CSCL I2C SCL Selected 4 USDSS USART D Slave Select Selected 5 TRACED3 TRACED3 Selected 6 TDQEPIDX Timer D QEP Index Selected 7 PG5 PG5 MUX Select 20 23 read-write GPIOG5 GPIO selected 0 TCPWM5 Timer C PWM5 Selected 1 TDPWM5 Timer D PWM5 Selected 2 EMUXC EMUX Clock Selected 3 USDMOSI USART D MOSI/TX Selected 5 CANRXD CAN RX Data Selected 6 TDQEPPHA Timer D QEP Phase A Selected 7 PG6 PG6 MUX Select 24 27 read-write GPIOG6 GPIO selected 0 TCPWM6 Timer C PWM6 Selected 1 TDPWM6 Timer D PWM6 Selected 2 I2CSDA I2C SDA Selected 3 USDMISO USART D MISO/RX Selected 5 CANTXD CAN TX Data Selected 6 TDQEPPHB Timer D QEP Phase B 7 PG7 PG7 MUX Select 28 31 read-write GPIOG7 GPIO selected 0 TDQEPIDX Timer D QEP Index Selected 2 USDSCLK USART D SPI Clock Selected 5 PGPDEN PG Weak Pull-down Enable 0x5C read-write n 0x0 0x0 PGPUEN PG Weak Pull-up Enable 0x40 read-write n 0x0 0x0 TimerA Timer A TimerA 0x0 0x0 0x10000 registers n TIMERA Timer A Interrupt 7 TIMERAQEP Timer A QEP Interrupt 11 CCTL0 Timer A CC Control 0 0x100 32 read-write n 0x0 0x0 CCFORCE Write 1 to force compare event (self-clearing) 7 8 read-write CCINTEDGE Capture Mode Interrupt Edge Setting 2 4 read-write Rising Rising Edge Interrupt 0 Falling Falling Edge Interrupt 1 Both Rising and Falling Edge Interrupt 2 CCINTEN CCR Interrupt Enable 1 2 read-write Disabled CCR interrupt disabled 0 Enabled CCR interrupt enabled 1 CCINTSKIP CC Interrupt Skip Counter 8 12 read-write Don't Skip Don't skip CCR matches before interrupt 0 Skip 1 Skip 1 CCR match before interrupt 1 Skip 10 Skip 10 CCR matches before interrupt 10 Skip 11 Skip 11 CCR matches before interrupt 11 Skip 12 Skip 12 CCR matches before interrupt 12 Skip 13 Skip 13 CCR matches before interrupt 13 Skip 14 Skip 14 CCR matches before interrupt 14 Skip 15 Skip 15 CCR matches before interrupt 15 Skip 2 Skip 2 CCR matches before interrupt 2 Skip 3 Skip 3 CCR matches before interrupt 3 Skip 4 Skip 4 CCR matches before interrupt 4 Skip 5 Skip 5 CCR matches before interrupt 5 Skip 6 Skip 6 CCR matches before interrupt 6 Skip 7 Skip 7 CCR matches before interrupt 7 Skip 8 Skip 8 CCR matches before interrupt 8 Skip 9 Skip 9 CCR matches before interrupt 9 CCLATCH CCR Register Latch Mode 5 7 read-write CTR=0/Rising Compare(latch on CTR=0)/ Capture(latch on rising edge) 0 CTR=Period/Falling Compare(latch on CTR=Period)/ Capture(latch on falling edge) 1 Immediate/Both Compare(latch immediately)/ Capture(latch on both edges) 2 CCOUTINV Invert CCR Output 4 5 read-write Not Inverted Do not invert CCR output 0 Inverted Invert CCR output 1 MODE CCR Mode 0 1 read-write Compare Compare Mode 0 Capture Capture Mode 1 CCTL1 Timer A CC Control 1 0x108 32 read-write n 0x0 0x0 CCFORCE Write 1 to force compare event (self-clearing) 7 8 read-write CCINTEDGE Capture Mode Interrupt Edge Setting 2 4 read-write Rising Rising Edge Interrupt 0 Falling Falling Edge Interrupt 1 Both Rising and Falling Edge Interrupt 2 CCINTEN CCR Interrupt Enable 1 2 read-write Disabled CCR interrupt disabled 0 Enabled CCR interrupt enabled 1 CCINTSKIP CC Interrupt Skip Counter 8 12 read-write Don't Skip Don't skip CCR matches before interrupt 0 Skip 1 Skip 1 CCR match before interrupt 1 Skip 10 Skip 10 CCR matches before interrupt 10 Skip 11 Skip 11 CCR matches before interrupt 11 Skip 12 Skip 12 CCR matches before interrupt 12 Skip 13 Skip 13 CCR matches before interrupt 13 Skip 14 Skip 14 CCR matches before interrupt 14 Skip 15 Skip 15 CCR matches before interrupt 15 Skip 2 Skip 2 CCR matches before interrupt 2 Skip 3 Skip 3 CCR matches before interrupt 3 Skip 4 Skip 4 CCR matches before interrupt 4 Skip 5 Skip 5 CCR matches before interrupt 5 Skip 6 Skip 6 CCR matches before interrupt 6 Skip 7 Skip 7 CCR matches before interrupt 7 Skip 8 Skip 8 CCR matches before interrupt 8 Skip 9 Skip 9 CCR matches before interrupt 9 CCLATCH CCR Register Latch Mode 5 7 read-write CTR=0/Rising Compare(latch on CTR=0)/ Capture(latch on rising edge) 0 CTR=Period/Falling Compare(latch on CTR=Period)/ Capture(latch on falling edge) 1 Immediate/Both Compare(latch immediately)/ Capture(latch on both edges) 2 CCOUTINV Invert CCR Output 4 5 read-write Not Inverted Do not invert CCR output 0 Inverted Invert CCR output 1 MODE CCR Mode 0 1 read-write Compare Compare Mode 0 Capture Capture Mode 1 CCTL2 Timer A CC Control 2 0x110 32 read-write n 0x0 0x0 CCFORCE Write 1 to force compare event (self-clearing) 7 8 read-write CCINTEDGE Capture Mode Interrupt Edge Setting 2 4 read-write Rising Rising Edge Interrupt 0 Falling Falling Edge Interrupt 1 Both Rising and Falling Edge Interrupt 2 CCINTEN CCR Interrupt Enable 1 2 read-write Disabled CCR interrupt disabled 0 Enabled CCR interrupt enabled 1 CCINTSKIP CC Interrupt Skip Counter 8 12 read-write Don't Skip Don't skip CCR matches before interrupt 0 Skip 1 Skip 1 CCR match before interrupt 1 Skip 10 Skip 10 CCR matches before interrupt 10 Skip 11 Skip 11 CCR matches before interrupt 11 Skip 12 Skip 12 CCR matches before interrupt 12 Skip 13 Skip 13 CCR matches before interrupt 13 Skip 14 Skip 14 CCR matches before interrupt 14 Skip 15 Skip 15 CCR matches before interrupt 15 Skip 2 Skip 2 CCR matches before interrupt 2 Skip 3 Skip 3 CCR matches before interrupt 3 Skip 4 Skip 4 CCR matches before interrupt 4 Skip 5 Skip 5 CCR matches before interrupt 5 Skip 6 Skip 6 CCR matches before interrupt 6 Skip 7 Skip 7 CCR matches before interrupt 7 Skip 8 Skip 8 CCR matches before interrupt 8 Skip 9 Skip 9 CCR matches before interrupt 9 CCLATCH CCR Register Latch Mode 5 7 read-write CTR=0/Rising Compare(latch on CTR=0)/ Capture(latch on rising edge) 0 CTR=Period/Falling Compare(latch on CTR=Period)/ Capture(latch on falling edge) 1 Immediate/Both Compare(latch immediately)/ Capture(latch on both edges) 2 CCOUTINV Invert CCR Output 4 5 read-write Not Inverted Do not invert CCR output 0 Inverted Invert CCR output 1 MODE CCR Mode 0 1 read-write Compare Compare Mode 0 Capture Capture Mode 1 CCTL3 Timer A CC Control 3 0x118 32 read-write n 0x0 0x0 CCFORCE Write 1 to force compare event (self-clearing) 7 8 read-write CCINTEDGE Capture Mode Interrupt Edge Setting 2 4 read-write Rising Rising Edge Interrupt 0 Falling Falling Edge Interrupt 1 Both Rising and Falling Edge Interrupt 2 CCINTEN CCR Interrupt Enable 1 2 read-write Disabled CCR interrupt disabled 0 Enabled CCR interrupt enabled 1 CCINTSKIP CC Interrupt Skip Counter 8 12 read-write Don't Skip Don't skip CCR matches before interrupt 0 Skip 1 Skip 1 CCR match before interrupt 1 Skip 10 Skip 10 CCR matches before interrupt 10 Skip 11 Skip 11 CCR matches before interrupt 11 Skip 12 Skip 12 CCR matches before interrupt 12 Skip 13 Skip 13 CCR matches before interrupt 13 Skip 14 Skip 14 CCR matches before interrupt 14 Skip 15 Skip 15 CCR matches before interrupt 15 Skip 2 Skip 2 CCR matches before interrupt 2 Skip 3 Skip 3 CCR matches before interrupt 3 Skip 4 Skip 4 CCR matches before interrupt 4 Skip 5 Skip 5 CCR matches before interrupt 5 Skip 6 Skip 6 CCR matches before interrupt 6 Skip 7 Skip 7 CCR matches before interrupt 7 Skip 8 Skip 8 CCR matches before interrupt 8 Skip 9 Skip 9 CCR matches before interrupt 9 CCLATCH CCR Register Latch Mode 5 7 read-write CTR=0/Rising Compare(latch on CTR=0)/ Capture(latch on rising edge) 0 CTR=Period/Falling Compare(latch on CTR=Period)/ Capture(latch on falling edge) 1 Immediate/Both Compare(latch immediately)/ Capture(latch on both edges) 2 CCOUTINV Invert CCR Output 4 5 read-write Not Inverted Do not invert CCR output 0 Inverted Invert CCR output 1 MODE CCR Mode 0 1 read-write Compare Compare Mode 0 Capture Capture Mode 1 CCTL4 Timer A CC Control 4 0x120 32 read-write n 0x0 0x0 CCFORCE Write 1 to force compare event (self-clearing) 7 8 read-write CCINTEDGE Capture Mode Interrupt Edge Setting 2 4 read-write Rising Rising Edge Interrupt 0 Falling Falling Edge Interrupt 1 Both Rising and Falling Edge Interrupt 2 CCINTEN CCR Interrupt Enable 1 2 read-write Disabled CCR interrupt disabled 0 Enabled CCR interrupt enabled 1 CCINTSKIP CC Interrupt Skip Counter 8 12 read-write Don't Skip Don't skip CCR matches before interrupt 0 Skip 1 Skip 1 CCR match before interrupt 1 Skip 10 Skip 10 CCR matches before interrupt 10 Skip 11 Skip 11 CCR matches before interrupt 11 Skip 12 Skip 12 CCR matches before interrupt 12 Skip 13 Skip 13 CCR matches before interrupt 13 Skip 14 Skip 14 CCR matches before interrupt 14 Skip 15 Skip 15 CCR matches before interrupt 15 Skip 2 Skip 2 CCR matches before interrupt 2 Skip 3 Skip 3 CCR matches before interrupt 3 Skip 4 Skip 4 CCR matches before interrupt 4 Skip 5 Skip 5 CCR matches before interrupt 5 Skip 6 Skip 6 CCR matches before interrupt 6 Skip 7 Skip 7 CCR matches before interrupt 7 Skip 8 Skip 8 CCR matches before interrupt 8 Skip 9 Skip 9 CCR matches before interrupt 9 CCLATCH CCR Register Latch Mode 5 7 read-write CTR=0/Rising Compare(latch on CTR=0)/ Capture(latch on rising edge) 0 CTR=Period/Falling Compare(latch on CTR=Period)/ Capture(latch on falling edge) 1 Immediate/Both Compare(latch immediately)/ Capture(latch on both edges) 2 CCOUTINV Invert CCR Output 4 5 read-write Not Inverted Do not invert CCR output 0 Inverted Invert CCR output 1 MODE CCR Mode 0 1 read-write Compare Compare Mode 0 Capture Capture Mode 1 CCTL5 Timer A CC Control 5 0x128 32 read-write n 0x0 0x0 CCFORCE Write 1 to force compare event (self-clearing) 7 8 read-write CCINTEDGE Capture Mode Interrupt Edge Setting 2 4 read-write Rising Rising Edge Interrupt 0 Falling Falling Edge Interrupt 1 Both Rising and Falling Edge Interrupt 2 CCINTEN CCR Interrupt Enable 1 2 read-write Disabled CCR interrupt disabled 0 Enabled CCR interrupt enabled 1 CCINTSKIP CC Interrupt Skip Counter 8 12 read-write Don't Skip Don't skip CCR matches before interrupt 0 Skip 1 Skip 1 CCR match before interrupt 1 Skip 10 Skip 10 CCR matches before interrupt 10 Skip 11 Skip 11 CCR matches before interrupt 11 Skip 12 Skip 12 CCR matches before interrupt 12 Skip 13 Skip 13 CCR matches before interrupt 13 Skip 14 Skip 14 CCR matches before interrupt 14 Skip 15 Skip 15 CCR matches before interrupt 15 Skip 2 Skip 2 CCR matches before interrupt 2 Skip 3 Skip 3 CCR matches before interrupt 3 Skip 4 Skip 4 CCR matches before interrupt 4 Skip 5 Skip 5 CCR matches before interrupt 5 Skip 6 Skip 6 CCR matches before interrupt 6 Skip 7 Skip 7 CCR matches before interrupt 7 Skip 8 Skip 8 CCR matches before interrupt 8 Skip 9 Skip 9 CCR matches before interrupt 9 CCLATCH CCR Register Latch Mode 5 7 read-write CTR=0/Rising Compare(latch on CTR=0)/ Capture(latch on rising edge) 0 CTR=Period/Falling Compare(latch on CTR=Period)/ Capture(latch on falling edge) 1 Immediate/Both Compare(latch immediately)/ Capture(latch on both edges) 2 CCOUTINV Invert CCR Output 4 5 read-write Not Inverted Do not invert CCR output 0 Inverted Invert CCR output 1 MODE CCR Mode 0 1 read-write Compare Compare Mode 0 Capture Capture Mode 1 CCTL6 Timer A CC Control 6 0x130 32 read-write n 0x0 0x0 CCFORCE Write 1 to force compare event (self-clearing) 7 8 read-write CCINTEDGE Capture Mode Interrupt Edge Setting 2 4 read-write Rising Rising Edge Interrupt 0 Falling Falling Edge Interrupt 1 Both Rising and Falling Edge Interrupt 2 CCINTEN CCR Interrupt Enable 1 2 read-write Disabled CCR interrupt disabled 0 Enabled CCR interrupt enabled 1 CCINTSKIP CC Interrupt Skip Counter 8 12 read-write Don't Skip Don't skip CCR matches before interrupt 0 Skip 1 Skip 1 CCR match before interrupt 1 Skip 10 Skip 10 CCR matches before interrupt 10 Skip 11 Skip 11 CCR matches before interrupt 11 Skip 12 Skip 12 CCR matches before interrupt 12 Skip 13 Skip 13 CCR matches before interrupt 13 Skip 14 Skip 14 CCR matches before interrupt 14 Skip 15 Skip 15 CCR matches before interrupt 15 Skip 2 Skip 2 CCR matches before interrupt 2 Skip 3 Skip 3 CCR matches before interrupt 3 Skip 4 Skip 4 CCR matches before interrupt 4 Skip 5 Skip 5 CCR matches before interrupt 5 Skip 6 Skip 6 CCR matches before interrupt 6 Skip 7 Skip 7 CCR matches before interrupt 7 Skip 8 Skip 8 CCR matches before interrupt 8 Skip 9 Skip 9 CCR matches before interrupt 9 CCLATCH CCR Register Latch Mode 5 7 read-write CTR=0/Rising Compare(latch on CTR=0)/ Capture(latch on rising edge) 0 CTR=Period/Falling Compare(latch on CTR=Period)/ Capture(latch on falling edge) 1 Immediate/Both Compare(latch immediately)/ Capture(latch on both edges) 2 CCOUTINV Invert CCR Output 4 5 read-write Not Inverted Do not invert CCR output 0 Inverted Invert CCR output 1 MODE CCR Mode 0 1 read-write Compare Compare Mode 0 Capture Capture Mode 1 CCTL7 Timer A CC Control 7 0x138 32 read-write n 0x0 0x0 CCFORCE Write 1 to force compare event (self-clearing) 7 8 read-write CCINTEDGE Capture Mode Interrupt Edge Setting 2 4 read-write Rising Rising Edge Interrupt 0 Falling Falling Edge Interrupt 1 Both Rising and Falling Edge Interrupt 2 CCINTEN CCR Interrupt Enable 1 2 read-write Disabled CCR interrupt disabled 0 Enabled CCR interrupt enabled 1 CCINTSKIP CC Interrupt Skip Counter 8 12 read-write Don't Skip Don't skip CCR matches before interrupt 0 Skip 1 Skip 1 CCR match before interrupt 1 Skip 10 Skip 10 CCR matches before interrupt 10 Skip 11 Skip 11 CCR matches before interrupt 11 Skip 12 Skip 12 CCR matches before interrupt 12 Skip 13 Skip 13 CCR matches before interrupt 13 Skip 14 Skip 14 CCR matches before interrupt 14 Skip 15 Skip 15 CCR matches before interrupt 15 Skip 2 Skip 2 CCR matches before interrupt 2 Skip 3 Skip 3 CCR matches before interrupt 3 Skip 4 Skip 4 CCR matches before interrupt 4 Skip 5 Skip 5 CCR matches before interrupt 5 Skip 6 Skip 6 CCR matches before interrupt 6 Skip 7 Skip 7 CCR matches before interrupt 7 Skip 8 Skip 8 CCR matches before interrupt 8 Skip 9 Skip 9 CCR matches before interrupt 9 CCLATCH CCR Register Latch Mode 5 7 read-write CTR=0/Rising Compare(latch on CTR=0)/ Capture(latch on rising edge) 0 CTR=Period/Falling Compare(latch on CTR=Period)/ Capture(latch on falling edge) 1 Immediate/Both Compare(latch immediately)/ Capture(latch on both edges) 2 CCOUTINV Invert CCR Output 4 5 read-write Not Inverted Do not invert CCR output 0 Inverted Invert CCR output 1 MODE CCR Mode 0 1 read-write Compare Compare Mode 0 Capture Capture Mode 1 CCTR0 Timer A CC Counter 0 0x104 read-write n 0x0 0x0 CCTR1 Timer A CC Counter 1 0x10C read-write n 0x0 0x0 CCTR2 Timer A CC Counter 2 0x114 read-write n 0x0 0x0 CCTR3 Timer A CC Counter 3 0x11C read-write n 0x0 0x0 CCTR4 Timer A CC Counter 4 0x124 read-write n 0x0 0x0 CCTR5 Timer A CC Counter 5 0x12C read-write n 0x0 0x0 CCTR6 Timer A CC Counter 6 0x134 read-write n 0x0 0x0 CCTR7 Timer A CC Counter 7 0x13C read-write n 0x0 0x0 CTL Timer A Control 0x0 32 read-write n 0x0 0x0 BASEIE Base timer interrupt enable 13 14 read-write Disabled Base interrupt disabled 0 Enabled Base interrupt enabled 1 CLKDIV Timer Input Clock Divider 6 9 read-write /1 Timer input clock /1 0 /2 Timer input clock /2 1 /4 Timer input clock /4 2 /8 Timer input clock /8 3 /16 Timer input clock /16 4 /32 Timer input clock /32 5 /64 Timer input clock /64 6 /128 Timer input clock /128 7 CLKSRC Timer Clock Source 9 10 read-write PCLK PCLK selected as input to timer 0 ACLK ACLK selected as input to timer 1 CLR Timer Clear 12 13 read-write Do Not Clear Do not clear timer counter 0 Clear Clear timer counter 1 DTGCLK Dead-Time Generator Clock Source 10 11 read-write Before Divider Before input clock divider 0 After Divider After input clock divider 1 LATCH Write 1 to Latch Period and all CCTRs 11 12 read-write MODE Timer Mode 0 2 read-write Disabled Disabled Mode 0 Up Up Mode 1 Up/Down Up/Down Mode 2 Asymmetric Asymmetric Mode 3 PRDLATCH Timer Period Latch Mode 2 4 read-write CTR=0 Period is latched when CTR = 0 0 CTR=Period Period is latched when CTR = Period 1 Immediate Period is latched immediately upon register write 2 SINGLE Single Shot Timer 5 6 read-write Disabled Single Shot Disabled (auto-reload) 0 Enabled Single Shot Timer Enabled 1 SSYNC Timer Slave Synchronization 4 5 read-write Disabled Slave Sync Disabled 0 Enabled Slave Sync Enabled 1 CTR Timer A Counter 0xC read-write n 0x0 0x0 DTGCTL0 Timer A DTG Control 0 0x200 read-write n 0x0 0x0 DTGCTL1 Timer A DTG Control 1 0x204 read-write n 0x0 0x0 DTGCTL2 Timer A DTG Control 2 0x208 read-write n 0x0 0x0 DTGCTL3 Timer A DTG Control 3 0x20C read-write n 0x0 0x0 INT Timer A Interrupt Control 0x4 read-write n 0x0 0x0 PRD Timer A Period 0x8 read-write n 0x0 0x0 QEPCTL Timer A QEP Control 0x10 read-write n 0x0 0x0 TimerB Timer B TimerB 0x0 0x0 0x10000 registers n TIMERB Timer B Interrupt 8 TIMERBQEP Timer B QEP Interrupt 12 CCTL0 Timer B CC Control 0 0x100 32 read-write n 0x0 0x0 CCFORCE Write 1 to force compare event (self-clearing) 7 8 read-write CCINTEDGE Capture Mode Interrupt Edge Setting 2 4 read-write Rising Rising Edge Interrupt 0 Falling Falling Edge Interrupt 1 Both Rising and Falling Edge Interrupt 2 CCINTEN CCR Interrupt Enable 1 2 read-write Disabled CCR interrupt disabled 0 Enabled CCR interrupt enabled 1 CCINTSKIP CC Interrupt Skip Counter 8 12 read-write Don't Skip Don't skip CCR matches before interrupt 0 Skip 1 Skip 1 CCR match before interrupt 1 Skip 10 Skip 10 CCR matches before interrupt 10 Skip 11 Skip 11 CCR matches before interrupt 11 Skip 12 Skip 12 CCR matches before interrupt 12 Skip 13 Skip 13 CCR matches before interrupt 13 Skip 14 Skip 14 CCR matches before interrupt 14 Skip 15 Skip 15 CCR matches before interrupt 15 Skip 2 Skip 2 CCR matches before interrupt 2 Skip 3 Skip 3 CCR matches before interrupt 3 Skip 4 Skip 4 CCR matches before interrupt 4 Skip 5 Skip 5 CCR matches before interrupt 5 Skip 6 Skip 6 CCR matches before interrupt 6 Skip 7 Skip 7 CCR matches before interrupt 7 Skip 8 Skip 8 CCR matches before interrupt 8 Skip 9 Skip 9 CCR matches before interrupt 9 CCLATCH CCR Register Latch Mode 5 7 read-write CTR=0/Rising Compare(latch on CTR=0)/ Capture(latch on rising edge) 0 CTR=Period/Falling Compare(latch on CTR=Period)/ Capture(latch on falling edge) 1 Immediate/Both Compare(latch immediately)/ Capture(latch on both edges) 2 CCOUTINV Invert CCR Output 4 5 read-write Not Inverted Do not invert CCR output 0 Inverted Invert CCR output 1 MODE CCR Mode 0 1 read-write Compare Compare Mode 0 Capture Capture Mode 1 CCTL1 Timer B CC Control 1 0x108 32 read-write n 0x0 0x0 CCFORCE Write 1 to force compare event (self-clearing) 7 8 read-write CCINTEDGE Capture Mode Interrupt Edge Setting 2 4 read-write Rising Rising Edge Interrupt 0 Falling Falling Edge Interrupt 1 Both Rising and Falling Edge Interrupt 2 CCINTEN CCR Interrupt Enable 1 2 read-write Disabled CCR interrupt disabled 0 Enabled CCR interrupt enabled 1 CCINTSKIP CC Interrupt Skip Counter 8 12 read-write Don't Skip Don't skip CCR matches before interrupt 0 Skip 1 Skip 1 CCR match before interrupt 1 Skip 10 Skip 10 CCR matches before interrupt 10 Skip 11 Skip 11 CCR matches before interrupt 11 Skip 12 Skip 12 CCR matches before interrupt 12 Skip 13 Skip 13 CCR matches before interrupt 13 Skip 14 Skip 14 CCR matches before interrupt 14 Skip 15 Skip 15 CCR matches before interrupt 15 Skip 2 Skip 2 CCR matches before interrupt 2 Skip 3 Skip 3 CCR matches before interrupt 3 Skip 4 Skip 4 CCR matches before interrupt 4 Skip 5 Skip 5 CCR matches before interrupt 5 Skip 6 Skip 6 CCR matches before interrupt 6 Skip 7 Skip 7 CCR matches before interrupt 7 Skip 8 Skip 8 CCR matches before interrupt 8 Skip 9 Skip 9 CCR matches before interrupt 9 CCLATCH CCR Register Latch Mode 5 7 read-write CTR=0/Rising Compare(latch on CTR=0)/ Capture(latch on rising edge) 0 CTR=Period/Falling Compare(latch on CTR=Period)/ Capture(latch on falling edge) 1 Immediate/Both Compare(latch immediately)/ Capture(latch on both edges) 2 CCOUTINV Invert CCR Output 4 5 read-write Not Inverted Do not invert CCR output 0 Inverted Invert CCR output 1 MODE CCR Mode 0 1 read-write Compare Compare Mode 0 Capture Capture Mode 1 CCTL2 Timer B CC Control 2 0x110 32 read-write n 0x0 0x0 CCFORCE Write 1 to force compare event (self-clearing) 7 8 read-write CCINTEDGE Capture Mode Interrupt Edge Setting 2 4 read-write Rising Rising Edge Interrupt 0 Falling Falling Edge Interrupt 1 Both Rising and Falling Edge Interrupt 2 CCINTEN CCR Interrupt Enable 1 2 read-write Disabled CCR interrupt disabled 0 Enabled CCR interrupt enabled 1 CCINTSKIP CC Interrupt Skip Counter 8 12 read-write Don't Skip Don't skip CCR matches before interrupt 0 Skip 1 Skip 1 CCR match before interrupt 1 Skip 10 Skip 10 CCR matches before interrupt 10 Skip 11 Skip 11 CCR matches before interrupt 11 Skip 12 Skip 12 CCR matches before interrupt 12 Skip 13 Skip 13 CCR matches before interrupt 13 Skip 14 Skip 14 CCR matches before interrupt 14 Skip 15 Skip 15 CCR matches before interrupt 15 Skip 2 Skip 2 CCR matches before interrupt 2 Skip 3 Skip 3 CCR matches before interrupt 3 Skip 4 Skip 4 CCR matches before interrupt 4 Skip 5 Skip 5 CCR matches before interrupt 5 Skip 6 Skip 6 CCR matches before interrupt 6 Skip 7 Skip 7 CCR matches before interrupt 7 Skip 8 Skip 8 CCR matches before interrupt 8 Skip 9 Skip 9 CCR matches before interrupt 9 CCLATCH CCR Register Latch Mode 5 7 read-write CTR=0/Rising Compare(latch on CTR=0)/ Capture(latch on rising edge) 0 CTR=Period/Falling Compare(latch on CTR=Period)/ Capture(latch on falling edge) 1 Immediate/Both Compare(latch immediately)/ Capture(latch on both edges) 2 CCOUTINV Invert CCR Output 4 5 read-write Not Inverted Do not invert CCR output 0 Inverted Invert CCR output 1 MODE CCR Mode 0 1 read-write Compare Compare Mode 0 Capture Capture Mode 1 CCTL3 Timer B CC Control 3 0x118 32 read-write n 0x0 0x0 CCFORCE Write 1 to force compare event (self-clearing) 7 8 read-write CCINTEDGE Capture Mode Interrupt Edge Setting 2 4 read-write Rising Rising Edge Interrupt 0 Falling Falling Edge Interrupt 1 Both Rising and Falling Edge Interrupt 2 CCINTEN CCR Interrupt Enable 1 2 read-write Disabled CCR interrupt disabled 0 Enabled CCR interrupt enabled 1 CCINTSKIP CC Interrupt Skip Counter 8 12 read-write Don't Skip Don't skip CCR matches before interrupt 0 Skip 1 Skip 1 CCR match before interrupt 1 Skip 10 Skip 10 CCR matches before interrupt 10 Skip 11 Skip 11 CCR matches before interrupt 11 Skip 12 Skip 12 CCR matches before interrupt 12 Skip 13 Skip 13 CCR matches before interrupt 13 Skip 14 Skip 14 CCR matches before interrupt 14 Skip 15 Skip 15 CCR matches before interrupt 15 Skip 2 Skip 2 CCR matches before interrupt 2 Skip 3 Skip 3 CCR matches before interrupt 3 Skip 4 Skip 4 CCR matches before interrupt 4 Skip 5 Skip 5 CCR matches before interrupt 5 Skip 6 Skip 6 CCR matches before interrupt 6 Skip 7 Skip 7 CCR matches before interrupt 7 Skip 8 Skip 8 CCR matches before interrupt 8 Skip 9 Skip 9 CCR matches before interrupt 9 CCLATCH CCR Register Latch Mode 5 7 read-write CTR=0/Rising Compare(latch on CTR=0)/ Capture(latch on rising edge) 0 CTR=Period/Falling Compare(latch on CTR=Period)/ Capture(latch on falling edge) 1 Immediate/Both Compare(latch immediately)/ Capture(latch on both edges) 2 CCOUTINV Invert CCR Output 4 5 read-write Not Inverted Do not invert CCR output 0 Inverted Invert CCR output 1 MODE CCR Mode 0 1 read-write Compare Compare Mode 0 Capture Capture Mode 1 CCTL4 Timer B CC Control 4 0x120 32 read-write n 0x0 0x0 CCFORCE Write 1 to force compare event (self-clearing) 7 8 read-write CCINTEDGE Capture Mode Interrupt Edge Setting 2 4 read-write Rising Rising Edge Interrupt 0 Falling Falling Edge Interrupt 1 Both Rising and Falling Edge Interrupt 2 CCINTEN CCR Interrupt Enable 1 2 read-write Disabled CCR interrupt disabled 0 Enabled CCR interrupt enabled 1 CCINTSKIP CC Interrupt Skip Counter 8 12 read-write Don't Skip Don't skip CCR matches before interrupt 0 Skip 1 Skip 1 CCR match before interrupt 1 Skip 10 Skip 10 CCR matches before interrupt 10 Skip 11 Skip 11 CCR matches before interrupt 11 Skip 12 Skip 12 CCR matches before interrupt 12 Skip 13 Skip 13 CCR matches before interrupt 13 Skip 14 Skip 14 CCR matches before interrupt 14 Skip 15 Skip 15 CCR matches before interrupt 15 Skip 2 Skip 2 CCR matches before interrupt 2 Skip 3 Skip 3 CCR matches before interrupt 3 Skip 4 Skip 4 CCR matches before interrupt 4 Skip 5 Skip 5 CCR matches before interrupt 5 Skip 6 Skip 6 CCR matches before interrupt 6 Skip 7 Skip 7 CCR matches before interrupt 7 Skip 8 Skip 8 CCR matches before interrupt 8 Skip 9 Skip 9 CCR matches before interrupt 9 CCLATCH CCR Register Latch Mode 5 7 read-write CTR=0/Rising Compare(latch on CTR=0)/ Capture(latch on rising edge) 0 CTR=Period/Falling Compare(latch on CTR=Period)/ Capture(latch on falling edge) 1 Immediate/Both Compare(latch immediately)/ Capture(latch on both edges) 2 CCOUTINV Invert CCR Output 4 5 read-write Not Inverted Do not invert CCR output 0 Inverted Invert CCR output 1 MODE CCR Mode 0 1 read-write Compare Compare Mode 0 Capture Capture Mode 1 CCTL5 Timer B CC Control 5 0x128 32 read-write n 0x0 0x0 CCFORCE Write 1 to force compare event (self-clearing) 7 8 read-write CCINTEDGE Capture Mode Interrupt Edge Setting 2 4 read-write Rising Rising Edge Interrupt 0 Falling Falling Edge Interrupt 1 Both Rising and Falling Edge Interrupt 2 CCINTEN CCR Interrupt Enable 1 2 read-write Disabled CCR interrupt disabled 0 Enabled CCR interrupt enabled 1 CCINTSKIP CC Interrupt Skip Counter 8 12 read-write Don't Skip Don't skip CCR matches before interrupt 0 Skip 1 Skip 1 CCR match before interrupt 1 Skip 10 Skip 10 CCR matches before interrupt 10 Skip 11 Skip 11 CCR matches before interrupt 11 Skip 12 Skip 12 CCR matches before interrupt 12 Skip 13 Skip 13 CCR matches before interrupt 13 Skip 14 Skip 14 CCR matches before interrupt 14 Skip 15 Skip 15 CCR matches before interrupt 15 Skip 2 Skip 2 CCR matches before interrupt 2 Skip 3 Skip 3 CCR matches before interrupt 3 Skip 4 Skip 4 CCR matches before interrupt 4 Skip 5 Skip 5 CCR matches before interrupt 5 Skip 6 Skip 6 CCR matches before interrupt 6 Skip 7 Skip 7 CCR matches before interrupt 7 Skip 8 Skip 8 CCR matches before interrupt 8 Skip 9 Skip 9 CCR matches before interrupt 9 CCLATCH CCR Register Latch Mode 5 7 read-write CTR=0/Rising Compare(latch on CTR=0)/ Capture(latch on rising edge) 0 CTR=Period/Falling Compare(latch on CTR=Period)/ Capture(latch on falling edge) 1 Immediate/Both Compare(latch immediately)/ Capture(latch on both edges) 2 CCOUTINV Invert CCR Output 4 5 read-write Not Inverted Do not invert CCR output 0 Inverted Invert CCR output 1 MODE CCR Mode 0 1 read-write Compare Compare Mode 0 Capture Capture Mode 1 CCTL6 Timer B CC Control 6 0x130 32 read-write n 0x0 0x0 CCFORCE Write 1 to force compare event (self-clearing) 7 8 read-write CCINTEDGE Capture Mode Interrupt Edge Setting 2 4 read-write Rising Rising Edge Interrupt 0 Falling Falling Edge Interrupt 1 Both Rising and Falling Edge Interrupt 2 CCINTEN CCR Interrupt Enable 1 2 read-write Disabled CCR interrupt disabled 0 Enabled CCR interrupt enabled 1 CCINTSKIP CC Interrupt Skip Counter 8 12 read-write Don't Skip Don't skip CCR matches before interrupt 0 Skip 1 Skip 1 CCR match before interrupt 1 Skip 10 Skip 10 CCR matches before interrupt 10 Skip 11 Skip 11 CCR matches before interrupt 11 Skip 12 Skip 12 CCR matches before interrupt 12 Skip 13 Skip 13 CCR matches before interrupt 13 Skip 14 Skip 14 CCR matches before interrupt 14 Skip 15 Skip 15 CCR matches before interrupt 15 Skip 2 Skip 2 CCR matches before interrupt 2 Skip 3 Skip 3 CCR matches before interrupt 3 Skip 4 Skip 4 CCR matches before interrupt 4 Skip 5 Skip 5 CCR matches before interrupt 5 Skip 6 Skip 6 CCR matches before interrupt 6 Skip 7 Skip 7 CCR matches before interrupt 7 Skip 8 Skip 8 CCR matches before interrupt 8 Skip 9 Skip 9 CCR matches before interrupt 9 CCLATCH CCR Register Latch Mode 5 7 read-write CTR=0/Rising Compare(latch on CTR=0)/ Capture(latch on rising edge) 0 CTR=Period/Falling Compare(latch on CTR=Period)/ Capture(latch on falling edge) 1 Immediate/Both Compare(latch immediately)/ Capture(latch on both edges) 2 CCOUTINV Invert CCR Output 4 5 read-write Not Inverted Do not invert CCR output 0 Inverted Invert CCR output 1 MODE CCR Mode 0 1 read-write Compare Compare Mode 0 Capture Capture Mode 1 CCTL7 Timer B CC Control 7 0x138 32 read-write n 0x0 0x0 CCFORCE Write 1 to force compare event (self-clearing) 7 8 read-write CCINTEDGE Capture Mode Interrupt Edge Setting 2 4 read-write Rising Rising Edge Interrupt 0 Falling Falling Edge Interrupt 1 Both Rising and Falling Edge Interrupt 2 CCINTEN CCR Interrupt Enable 1 2 read-write Disabled CCR interrupt disabled 0 Enabled CCR interrupt enabled 1 CCINTSKIP CC Interrupt Skip Counter 8 12 read-write Don't Skip Don't skip CCR matches before interrupt 0 Skip 1 Skip 1 CCR match before interrupt 1 Skip 10 Skip 10 CCR matches before interrupt 10 Skip 11 Skip 11 CCR matches before interrupt 11 Skip 12 Skip 12 CCR matches before interrupt 12 Skip 13 Skip 13 CCR matches before interrupt 13 Skip 14 Skip 14 CCR matches before interrupt 14 Skip 15 Skip 15 CCR matches before interrupt 15 Skip 2 Skip 2 CCR matches before interrupt 2 Skip 3 Skip 3 CCR matches before interrupt 3 Skip 4 Skip 4 CCR matches before interrupt 4 Skip 5 Skip 5 CCR matches before interrupt 5 Skip 6 Skip 6 CCR matches before interrupt 6 Skip 7 Skip 7 CCR matches before interrupt 7 Skip 8 Skip 8 CCR matches before interrupt 8 Skip 9 Skip 9 CCR matches before interrupt 9 CCLATCH CCR Register Latch Mode 5 7 read-write CTR=0/Rising Compare(latch on CTR=0)/ Capture(latch on rising edge) 0 CTR=Period/Falling Compare(latch on CTR=Period)/ Capture(latch on falling edge) 1 Immediate/Both Compare(latch immediately)/ Capture(latch on both edges) 2 CCOUTINV Invert CCR Output 4 5 read-write Not Inverted Do not invert CCR output 0 Inverted Invert CCR output 1 MODE CCR Mode 0 1 read-write Compare Compare Mode 0 Capture Capture Mode 1 CCTR0 Timer B CC Counter 0 0x104 read-write n 0x0 0x0 CCTR1 Timer B CC Counter 1 0x10C read-write n 0x0 0x0 CCTR2 Timer B CC Counter 2 0x114 read-write n 0x0 0x0 CCTR3 Timer B CC Counter 3 0x11C read-write n 0x0 0x0 CCTR4 Timer B CC Counter 4 0x124 read-write n 0x0 0x0 CCTR5 Timer B CC Counter 5 0x12C read-write n 0x0 0x0 CCTR6 Timer B CC Counter 6 0x134 read-write n 0x0 0x0 CCTR7 Timer B CC Counter 7 0x13C read-write n 0x0 0x0 CTL Timer B Control 0x0 32 read-write n 0x0 0x0 BASEIE Base timer interrupt enable 13 14 read-write Disabled Base interrupt disabled 0 Enabled Base interrupt enabled 1 CLKDIV Timer Input Clock Divider 6 9 read-write /1 Timer input clock /1 0 /2 Timer input clock /2 1 /4 Timer input clock /4 2 /8 Timer input clock /8 3 /16 Timer input clock /16 4 /32 Timer input clock /32 5 /64 Timer input clock /64 6 /128 Timer input clock /128 7 CLKSRC Timer Clock Source 9 10 read-write PCLK PCLK selected as input to timer 0 ACLK ACLK selected as input to timer 1 CLR Timer Clear 12 13 read-write Do Not Clear Do not clear timer counter 0 Clear Clear timer counter 1 DTGCLK Dead-Time Generator Clock Source 10 11 read-write Before Divider Before input clock divider 0 After Divider After input clock divider 1 LATCH Write 1 to Latch Period and all CCTRs 11 12 read-write MODE Timer Mode 0 2 read-write Disabled Disabled Mode 0 Up Up Mode 1 Up/Down Up/Down Mode 2 Asymmetric Asymmetric Mode 3 PRDLATCH Timer Period Latch Mode 2 4 read-write CTR=0 Period is latched when CTR = 0 0 CTR=Period Period is latched when CTR = Period 1 Immediate Period is latched immediately upon register write 2 SINGLE Single Shot Timer 5 6 read-write Disabled Single Shot Disabled (auto-reload) 0 Enabled Single Shot Timer Enabled 1 SSYNC Timer Slave Synchronization 4 5 read-write Disabled Slave Sync Disabled 0 Enabled Slave Sync Enabled 1 CTR Timer B Counter 0xC read-write n 0x0 0x0 DTGCTL0 Timer B DTG Control 0 0x200 read-write n 0x0 0x0 DTGCTL1 Timer B DTG Control 1 0x204 read-write n 0x0 0x0 DTGCTL2 Timer B DTG Control 2 0x208 read-write n 0x0 0x0 DTGCTL3 Timer B DTG Control 3 0x20C read-write n 0x0 0x0 INT Timer B Interrupt Control 0x4 read-write n 0x0 0x0 PRD Timer B Period 0x8 read-write n 0x0 0x0 QEPCTL Timer B QEP Control 0x10 read-write n 0x0 0x0 TimerC Timer C TimerC 0x0 0x0 0x10000 registers n TIMERC Timer C Interrupt 9 TIMERCQEP Timer C QEP Interrupt 13 CCTL0 Timer C CC Control 0 0x100 32 read-write n 0x0 0x0 CCFORCE Write 1 to force compare event (self-clearing) 7 8 read-write CCINTEDGE Capture Mode Interrupt Edge Setting 2 4 read-write Rising Rising Edge Interrupt 0 Falling Falling Edge Interrupt 1 Both Rising and Falling Edge Interrupt 2 CCINTEN CCR Interrupt Enable 1 2 read-write Disabled CCR interrupt disabled 0 Enabled CCR interrupt enabled 1 CCINTSKIP CC Interrupt Skip Counter 8 12 read-write Don't Skip Don't skip CCR matches before interrupt 0 Skip 1 Skip 1 CCR match before interrupt 1 Skip 10 Skip 10 CCR matches before interrupt 10 Skip 11 Skip 11 CCR matches before interrupt 11 Skip 12 Skip 12 CCR matches before interrupt 12 Skip 13 Skip 13 CCR matches before interrupt 13 Skip 14 Skip 14 CCR matches before interrupt 14 Skip 15 Skip 15 CCR matches before interrupt 15 Skip 2 Skip 2 CCR matches before interrupt 2 Skip 3 Skip 3 CCR matches before interrupt 3 Skip 4 Skip 4 CCR matches before interrupt 4 Skip 5 Skip 5 CCR matches before interrupt 5 Skip 6 Skip 6 CCR matches before interrupt 6 Skip 7 Skip 7 CCR matches before interrupt 7 Skip 8 Skip 8 CCR matches before interrupt 8 Skip 9 Skip 9 CCR matches before interrupt 9 CCLATCH CCR Register Latch Mode 5 7 read-write CTR=0/Rising Compare(latch on CTR=0)/ Capture(latch on rising edge) 0 CTR=Period/Falling Compare(latch on CTR=Period)/ Capture(latch on falling edge) 1 Immediate/Both Compare(latch immediately)/ Capture(latch on both edges) 2 CCOUTINV Invert CCR Output 4 5 read-write Not Inverted Do not invert CCR output 0 Inverted Invert CCR output 1 MODE CCR Mode 0 1 read-write Compare Compare Mode 0 Capture Capture Mode 1 CCTL1 Timer C CC Control 1 0x108 32 read-write n 0x0 0x0 CCFORCE Write 1 to force compare event (self-clearing) 7 8 read-write CCINTEDGE Capture Mode Interrupt Edge Setting 2 4 read-write Rising Rising Edge Interrupt 0 Falling Falling Edge Interrupt 1 Both Rising and Falling Edge Interrupt 2 CCINTEN CCR Interrupt Enable 1 2 read-write Disabled CCR interrupt disabled 0 Enabled CCR interrupt enabled 1 CCINTSKIP CC Interrupt Skip Counter 8 12 read-write Don't Skip Don't skip CCR matches before interrupt 0 Skip 1 Skip 1 CCR match before interrupt 1 Skip 10 Skip 10 CCR matches before interrupt 10 Skip 11 Skip 11 CCR matches before interrupt 11 Skip 12 Skip 12 CCR matches before interrupt 12 Skip 13 Skip 13 CCR matches before interrupt 13 Skip 14 Skip 14 CCR matches before interrupt 14 Skip 15 Skip 15 CCR matches before interrupt 15 Skip 2 Skip 2 CCR matches before interrupt 2 Skip 3 Skip 3 CCR matches before interrupt 3 Skip 4 Skip 4 CCR matches before interrupt 4 Skip 5 Skip 5 CCR matches before interrupt 5 Skip 6 Skip 6 CCR matches before interrupt 6 Skip 7 Skip 7 CCR matches before interrupt 7 Skip 8 Skip 8 CCR matches before interrupt 8 Skip 9 Skip 9 CCR matches before interrupt 9 CCLATCH CCR Register Latch Mode 5 7 read-write CTR=0/Rising Compare(latch on CTR=0)/ Capture(latch on rising edge) 0 CTR=Period/Falling Compare(latch on CTR=Period)/ Capture(latch on falling edge) 1 Immediate/Both Compare(latch immediately)/ Capture(latch on both edges) 2 CCOUTINV Invert CCR Output 4 5 read-write Not Inverted Do not invert CCR output 0 Inverted Invert CCR output 1 MODE CCR Mode 0 1 read-write Compare Compare Mode 0 Capture Capture Mode 1 CCTL2 Timer C CC Control 2 0x110 32 read-write n 0x0 0x0 CCFORCE Write 1 to force compare event (self-clearing) 7 8 read-write CCINTEDGE Capture Mode Interrupt Edge Setting 2 4 read-write Rising Rising Edge Interrupt 0 Falling Falling Edge Interrupt 1 Both Rising and Falling Edge Interrupt 2 CCINTEN CCR Interrupt Enable 1 2 read-write Disabled CCR interrupt disabled 0 Enabled CCR interrupt enabled 1 CCINTSKIP CC Interrupt Skip Counter 8 12 read-write Don't Skip Don't skip CCR matches before interrupt 0 Skip 1 Skip 1 CCR match before interrupt 1 Skip 10 Skip 10 CCR matches before interrupt 10 Skip 11 Skip 11 CCR matches before interrupt 11 Skip 12 Skip 12 CCR matches before interrupt 12 Skip 13 Skip 13 CCR matches before interrupt 13 Skip 14 Skip 14 CCR matches before interrupt 14 Skip 15 Skip 15 CCR matches before interrupt 15 Skip 2 Skip 2 CCR matches before interrupt 2 Skip 3 Skip 3 CCR matches before interrupt 3 Skip 4 Skip 4 CCR matches before interrupt 4 Skip 5 Skip 5 CCR matches before interrupt 5 Skip 6 Skip 6 CCR matches before interrupt 6 Skip 7 Skip 7 CCR matches before interrupt 7 Skip 8 Skip 8 CCR matches before interrupt 8 Skip 9 Skip 9 CCR matches before interrupt 9 CCLATCH CCR Register Latch Mode 5 7 read-write CTR=0/Rising Compare(latch on CTR=0)/ Capture(latch on rising edge) 0 CTR=Period/Falling Compare(latch on CTR=Period)/ Capture(latch on falling edge) 1 Immediate/Both Compare(latch immediately)/ Capture(latch on both edges) 2 CCOUTINV Invert CCR Output 4 5 read-write Not Inverted Do not invert CCR output 0 Inverted Invert CCR output 1 MODE CCR Mode 0 1 read-write Compare Compare Mode 0 Capture Capture Mode 1 CCTL3 Timer C CC Control 3 0x118 32 read-write n 0x0 0x0 CCFORCE Write 1 to force compare event (self-clearing) 7 8 read-write CCINTEDGE Capture Mode Interrupt Edge Setting 2 4 read-write Rising Rising Edge Interrupt 0 Falling Falling Edge Interrupt 1 Both Rising and Falling Edge Interrupt 2 CCINTEN CCR Interrupt Enable 1 2 read-write Disabled CCR interrupt disabled 0 Enabled CCR interrupt enabled 1 CCINTSKIP CC Interrupt Skip Counter 8 12 read-write Don't Skip Don't skip CCR matches before interrupt 0 Skip 1 Skip 1 CCR match before interrupt 1 Skip 10 Skip 10 CCR matches before interrupt 10 Skip 11 Skip 11 CCR matches before interrupt 11 Skip 12 Skip 12 CCR matches before interrupt 12 Skip 13 Skip 13 CCR matches before interrupt 13 Skip 14 Skip 14 CCR matches before interrupt 14 Skip 15 Skip 15 CCR matches before interrupt 15 Skip 2 Skip 2 CCR matches before interrupt 2 Skip 3 Skip 3 CCR matches before interrupt 3 Skip 4 Skip 4 CCR matches before interrupt 4 Skip 5 Skip 5 CCR matches before interrupt 5 Skip 6 Skip 6 CCR matches before interrupt 6 Skip 7 Skip 7 CCR matches before interrupt 7 Skip 8 Skip 8 CCR matches before interrupt 8 Skip 9 Skip 9 CCR matches before interrupt 9 CCLATCH CCR Register Latch Mode 5 7 read-write CTR=0/Rising Compare(latch on CTR=0)/ Capture(latch on rising edge) 0 CTR=Period/Falling Compare(latch on CTR=Period)/ Capture(latch on falling edge) 1 Immediate/Both Compare(latch immediately)/ Capture(latch on both edges) 2 CCOUTINV Invert CCR Output 4 5 read-write Not Inverted Do not invert CCR output 0 Inverted Invert CCR output 1 MODE CCR Mode 0 1 read-write Compare Compare Mode 0 Capture Capture Mode 1 CCTL4 Timer C CC Control 4 0x120 32 read-write n 0x0 0x0 CCFORCE Write 1 to force compare event (self-clearing) 7 8 read-write CCINTEDGE Capture Mode Interrupt Edge Setting 2 4 read-write Rising Rising Edge Interrupt 0 Falling Falling Edge Interrupt 1 Both Rising and Falling Edge Interrupt 2 CCINTEN CCR Interrupt Enable 1 2 read-write Disabled CCR interrupt disabled 0 Enabled CCR interrupt enabled 1 CCINTSKIP CC Interrupt Skip Counter 8 12 read-write Don't Skip Don't skip CCR matches before interrupt 0 Skip 1 Skip 1 CCR match before interrupt 1 Skip 10 Skip 10 CCR matches before interrupt 10 Skip 11 Skip 11 CCR matches before interrupt 11 Skip 12 Skip 12 CCR matches before interrupt 12 Skip 13 Skip 13 CCR matches before interrupt 13 Skip 14 Skip 14 CCR matches before interrupt 14 Skip 15 Skip 15 CCR matches before interrupt 15 Skip 2 Skip 2 CCR matches before interrupt 2 Skip 3 Skip 3 CCR matches before interrupt 3 Skip 4 Skip 4 CCR matches before interrupt 4 Skip 5 Skip 5 CCR matches before interrupt 5 Skip 6 Skip 6 CCR matches before interrupt 6 Skip 7 Skip 7 CCR matches before interrupt 7 Skip 8 Skip 8 CCR matches before interrupt 8 Skip 9 Skip 9 CCR matches before interrupt 9 CCLATCH CCR Register Latch Mode 5 7 read-write CTR=0/Rising Compare(latch on CTR=0)/ Capture(latch on rising edge) 0 CTR=Period/Falling Compare(latch on CTR=Period)/ Capture(latch on falling edge) 1 Immediate/Both Compare(latch immediately)/ Capture(latch on both edges) 2 CCOUTINV Invert CCR Output 4 5 read-write Not Inverted Do not invert CCR output 0 Inverted Invert CCR output 1 MODE CCR Mode 0 1 read-write Compare Compare Mode 0 Capture Capture Mode 1 CCTL5 Timer C CC Control 5 0x128 32 read-write n 0x0 0x0 CCFORCE Write 1 to force compare event (self-clearing) 7 8 read-write CCINTEDGE Capture Mode Interrupt Edge Setting 2 4 read-write Rising Rising Edge Interrupt 0 Falling Falling Edge Interrupt 1 Both Rising and Falling Edge Interrupt 2 CCINTEN CCR Interrupt Enable 1 2 read-write Disabled CCR interrupt disabled 0 Enabled CCR interrupt enabled 1 CCINTSKIP CC Interrupt Skip Counter 8 12 read-write Don't Skip Don't skip CCR matches before interrupt 0 Skip 1 Skip 1 CCR match before interrupt 1 Skip 10 Skip 10 CCR matches before interrupt 10 Skip 11 Skip 11 CCR matches before interrupt 11 Skip 12 Skip 12 CCR matches before interrupt 12 Skip 13 Skip 13 CCR matches before interrupt 13 Skip 14 Skip 14 CCR matches before interrupt 14 Skip 15 Skip 15 CCR matches before interrupt 15 Skip 2 Skip 2 CCR matches before interrupt 2 Skip 3 Skip 3 CCR matches before interrupt 3 Skip 4 Skip 4 CCR matches before interrupt 4 Skip 5 Skip 5 CCR matches before interrupt 5 Skip 6 Skip 6 CCR matches before interrupt 6 Skip 7 Skip 7 CCR matches before interrupt 7 Skip 8 Skip 8 CCR matches before interrupt 8 Skip 9 Skip 9 CCR matches before interrupt 9 CCLATCH CCR Register Latch Mode 5 7 read-write CTR=0/Rising Compare(latch on CTR=0)/ Capture(latch on rising edge) 0 CTR=Period/Falling Compare(latch on CTR=Period)/ Capture(latch on falling edge) 1 Immediate/Both Compare(latch immediately)/ Capture(latch on both edges) 2 CCOUTINV Invert CCR Output 4 5 read-write Not Inverted Do not invert CCR output 0 Inverted Invert CCR output 1 MODE CCR Mode 0 1 read-write Compare Compare Mode 0 Capture Capture Mode 1 CCTL6 Timer C CC Control 6 0x130 32 read-write n 0x0 0x0 CCFORCE Write 1 to force compare event (self-clearing) 7 8 read-write CCINTEDGE Capture Mode Interrupt Edge Setting 2 4 read-write Rising Rising Edge Interrupt 0 Falling Falling Edge Interrupt 1 Both Rising and Falling Edge Interrupt 2 CCINTEN CCR Interrupt Enable 1 2 read-write Disabled CCR interrupt disabled 0 Enabled CCR interrupt enabled 1 CCINTSKIP CC Interrupt Skip Counter 8 12 read-write Don't Skip Don't skip CCR matches before interrupt 0 Skip 1 Skip 1 CCR match before interrupt 1 Skip 10 Skip 10 CCR matches before interrupt 10 Skip 11 Skip 11 CCR matches before interrupt 11 Skip 12 Skip 12 CCR matches before interrupt 12 Skip 13 Skip 13 CCR matches before interrupt 13 Skip 14 Skip 14 CCR matches before interrupt 14 Skip 15 Skip 15 CCR matches before interrupt 15 Skip 2 Skip 2 CCR matches before interrupt 2 Skip 3 Skip 3 CCR matches before interrupt 3 Skip 4 Skip 4 CCR matches before interrupt 4 Skip 5 Skip 5 CCR matches before interrupt 5 Skip 6 Skip 6 CCR matches before interrupt 6 Skip 7 Skip 7 CCR matches before interrupt 7 Skip 8 Skip 8 CCR matches before interrupt 8 Skip 9 Skip 9 CCR matches before interrupt 9 CCLATCH CCR Register Latch Mode 5 7 read-write CTR=0/Rising Compare(latch on CTR=0)/ Capture(latch on rising edge) 0 CTR=Period/Falling Compare(latch on CTR=Period)/ Capture(latch on falling edge) 1 Immediate/Both Compare(latch immediately)/ Capture(latch on both edges) 2 CCOUTINV Invert CCR Output 4 5 read-write Not Inverted Do not invert CCR output 0 Inverted Invert CCR output 1 MODE CCR Mode 0 1 read-write Compare Compare Mode 0 Capture Capture Mode 1 CCTL7 Timer C CC Control 7 0x138 32 read-write n 0x0 0x0 CCFORCE Write 1 to force compare event (self-clearing) 7 8 read-write CCINTEDGE Capture Mode Interrupt Edge Setting 2 4 read-write Rising Rising Edge Interrupt 0 Falling Falling Edge Interrupt 1 Both Rising and Falling Edge Interrupt 2 CCINTEN CCR Interrupt Enable 1 2 read-write Disabled CCR interrupt disabled 0 Enabled CCR interrupt enabled 1 CCINTSKIP CC Interrupt Skip Counter 8 12 read-write Don't Skip Don't skip CCR matches before interrupt 0 Skip 1 Skip 1 CCR match before interrupt 1 Skip 10 Skip 10 CCR matches before interrupt 10 Skip 11 Skip 11 CCR matches before interrupt 11 Skip 12 Skip 12 CCR matches before interrupt 12 Skip 13 Skip 13 CCR matches before interrupt 13 Skip 14 Skip 14 CCR matches before interrupt 14 Skip 15 Skip 15 CCR matches before interrupt 15 Skip 2 Skip 2 CCR matches before interrupt 2 Skip 3 Skip 3 CCR matches before interrupt 3 Skip 4 Skip 4 CCR matches before interrupt 4 Skip 5 Skip 5 CCR matches before interrupt 5 Skip 6 Skip 6 CCR matches before interrupt 6 Skip 7 Skip 7 CCR matches before interrupt 7 Skip 8 Skip 8 CCR matches before interrupt 8 Skip 9 Skip 9 CCR matches before interrupt 9 CCLATCH CCR Register Latch Mode 5 7 read-write CTR=0/Rising Compare(latch on CTR=0)/ Capture(latch on rising edge) 0 CTR=Period/Falling Compare(latch on CTR=Period)/ Capture(latch on falling edge) 1 Immediate/Both Compare(latch immediately)/ Capture(latch on both edges) 2 CCOUTINV Invert CCR Output 4 5 read-write Not Inverted Do not invert CCR output 0 Inverted Invert CCR output 1 MODE CCR Mode 0 1 read-write Compare Compare Mode 0 Capture Capture Mode 1 CCTR0 Timer C CC Counter 0 0x104 read-write n 0x0 0x0 CCTR1 Timer C CC Counter 1 0x10C read-write n 0x0 0x0 CCTR2 Timer C CC Counter 2 0x114 read-write n 0x0 0x0 CCTR3 Timer C CC Counter 3 0x11C read-write n 0x0 0x0 CCTR4 Timer C CC Counter 4 0x124 read-write n 0x0 0x0 CCTR5 Timer C CC Counter 5 0x12C read-write n 0x0 0x0 CCTR6 Timer C CC Counter 6 0x134 read-write n 0x0 0x0 CCTR7 Timer C CC Counter 7 0x13C read-write n 0x0 0x0 CTL Timer C Control 0x0 32 read-write n 0x0 0x0 BASEIE Base timer interrupt enable 13 14 read-write Disabled Base interrupt disabled 0 Enabled Base interrupt enabled 1 CLKDIV Timer Input Clock Divider 6 9 read-write /1 Timer input clock /1 0 /2 Timer input clock /2 1 /4 Timer input clock /4 2 /8 Timer input clock /8 3 /16 Timer input clock /16 4 /32 Timer input clock /32 5 /64 Timer input clock /64 6 /128 Timer input clock /128 7 CLKSRC Timer Clock Source 9 10 read-write PCLK PCLK selected as input to timer 0 ACLK ACLK selected as input to timer 1 CLR Timer Clear 12 13 read-write Do Not Clear Do not clear timer counter 0 Clear Clear timer counter 1 DTGCLK Dead-Time Generator Clock Source 10 11 read-write Before Divider Before input clock divider 0 After Divider After input clock divider 1 LATCH Write 1 to Latch Period and all CCTRs 11 12 read-write MODE Timer Mode 0 2 read-write Disabled Disabled Mode 0 Up Up Mode 1 Up/Down Up/Down Mode 2 Asymmetric Asymmetric Mode 3 PRDLATCH Timer Period Latch Mode 2 4 read-write CTR=0 Period is latched when CTR = 0 0 CTR=Period Period is latched when CTR = Period 1 Immediate Period is latched immediately upon register write 2 SINGLE Single Shot Timer 5 6 read-write Disabled Single Shot Disabled (auto-reload) 0 Enabled Single Shot Timer Enabled 1 SSYNC Timer Slave Synchronization 4 5 read-write Disabled Slave Sync Disabled 0 Enabled Slave Sync Enabled 1 CTR Timer C Counter 0xC read-write n 0x0 0x0 DTGCTL0 Timer C DTG Control 0 0x200 read-write n 0x0 0x0 DTGCTL1 Timer C DTG Control 1 0x204 read-write n 0x0 0x0 DTGCTL2 Timer C DTG Control 2 0x208 read-write n 0x0 0x0 DTGCTL3 Timer C DTG Control 3 0x20C read-write n 0x0 0x0 INT Timer C Interrupt Control 0x4 read-write n 0x0 0x0 PRD Timer C Period 0x8 read-write n 0x0 0x0 QEPCTL Timer C QEP Control 0x10 read-write n 0x0 0x0 TimerD Timer D TimerD 0x0 0x0 0x10000 registers n TIMERD Timer D Interrupt 10 TIMERDQEP Timer D QEP Interrupt 14 CCTL0 Timer D CC Control 0 0x100 32 read-write n 0x0 0x0 CCFORCE Write 1 to force compare event (self-clearing) 7 8 read-write CCINTEDGE Capture Mode Interrupt Edge Setting 2 4 read-write Rising Rising Edge Interrupt 0 Falling Falling Edge Interrupt 1 Both Rising and Falling Edge Interrupt 2 CCINTEN CCR Interrupt Enable 1 2 read-write Disabled CCR interrupt disabled 0 Enabled CCR interrupt enabled 1 CCINTSKIP CC Interrupt Skip Counter 8 12 read-write Don't Skip Don't skip CCR matches before interrupt 0 Skip 1 Skip 1 CCR match before interrupt 1 Skip 10 Skip 10 CCR matches before interrupt 10 Skip 11 Skip 11 CCR matches before interrupt 11 Skip 12 Skip 12 CCR matches before interrupt 12 Skip 13 Skip 13 CCR matches before interrupt 13 Skip 14 Skip 14 CCR matches before interrupt 14 Skip 15 Skip 15 CCR matches before interrupt 15 Skip 2 Skip 2 CCR matches before interrupt 2 Skip 3 Skip 3 CCR matches before interrupt 3 Skip 4 Skip 4 CCR matches before interrupt 4 Skip 5 Skip 5 CCR matches before interrupt 5 Skip 6 Skip 6 CCR matches before interrupt 6 Skip 7 Skip 7 CCR matches before interrupt 7 Skip 8 Skip 8 CCR matches before interrupt 8 Skip 9 Skip 9 CCR matches before interrupt 9 CCLATCH CCR Register Latch Mode 5 7 read-write CTR=0/Rising Compare(latch on CTR=0)/ Capture(latch on rising edge) 0 CTR=Period/Falling Compare(latch on CTR=Period)/ Capture(latch on falling edge) 1 Immediate/Both Compare(latch immediately)/ Capture(latch on both edges) 2 CCOUTINV Invert CCR Output 4 5 read-write Not Inverted Do not invert CCR output 0 Inverted Invert CCR output 1 MODE CCR Mode 0 1 read-write Compare Compare Mode 0 Capture Capture Mode 1 CCTL1 Timer D CC Control 1 0x108 32 read-write n 0x0 0x0 CCFORCE Write 1 to force compare event (self-clearing) 7 8 read-write CCINTEDGE Capture Mode Interrupt Edge Setting 2 4 read-write Rising Rising Edge Interrupt 0 Falling Falling Edge Interrupt 1 Both Rising and Falling Edge Interrupt 2 CCINTEN CCR Interrupt Enable 1 2 read-write Disabled CCR interrupt disabled 0 Enabled CCR interrupt enabled 1 CCINTSKIP CC Interrupt Skip Counter 8 12 read-write Don't Skip Don't skip CCR matches before interrupt 0 Skip 1 Skip 1 CCR match before interrupt 1 Skip 10 Skip 10 CCR matches before interrupt 10 Skip 11 Skip 11 CCR matches before interrupt 11 Skip 12 Skip 12 CCR matches before interrupt 12 Skip 13 Skip 13 CCR matches before interrupt 13 Skip 14 Skip 14 CCR matches before interrupt 14 Skip 15 Skip 15 CCR matches before interrupt 15 Skip 2 Skip 2 CCR matches before interrupt 2 Skip 3 Skip 3 CCR matches before interrupt 3 Skip 4 Skip 4 CCR matches before interrupt 4 Skip 5 Skip 5 CCR matches before interrupt 5 Skip 6 Skip 6 CCR matches before interrupt 6 Skip 7 Skip 7 CCR matches before interrupt 7 Skip 8 Skip 8 CCR matches before interrupt 8 Skip 9 Skip 9 CCR matches before interrupt 9 CCLATCH CCR Register Latch Mode 5 7 read-write CTR=0/Rising Compare(latch on CTR=0)/ Capture(latch on rising edge) 0 CTR=Period/Falling Compare(latch on CTR=Period)/ Capture(latch on falling edge) 1 Immediate/Both Compare(latch immediately)/ Capture(latch on both edges) 2 CCOUTINV Invert CCR Output 4 5 read-write Not Inverted Do not invert CCR output 0 Inverted Invert CCR output 1 MODE CCR Mode 0 1 read-write Compare Compare Mode 0 Capture Capture Mode 1 CCTL2 Timer D CC Control 2 0x110 32 read-write n 0x0 0x0 CCFORCE Write 1 to force compare event (self-clearing) 7 8 read-write CCINTEDGE Capture Mode Interrupt Edge Setting 2 4 read-write Rising Rising Edge Interrupt 0 Falling Falling Edge Interrupt 1 Both Rising and Falling Edge Interrupt 2 CCINTEN CCR Interrupt Enable 1 2 read-write Disabled CCR interrupt disabled 0 Enabled CCR interrupt enabled 1 CCINTSKIP CC Interrupt Skip Counter 8 12 read-write Don't Skip Don't skip CCR matches before interrupt 0 Skip 1 Skip 1 CCR match before interrupt 1 Skip 10 Skip 10 CCR matches before interrupt 10 Skip 11 Skip 11 CCR matches before interrupt 11 Skip 12 Skip 12 CCR matches before interrupt 12 Skip 13 Skip 13 CCR matches before interrupt 13 Skip 14 Skip 14 CCR matches before interrupt 14 Skip 15 Skip 15 CCR matches before interrupt 15 Skip 2 Skip 2 CCR matches before interrupt 2 Skip 3 Skip 3 CCR matches before interrupt 3 Skip 4 Skip 4 CCR matches before interrupt 4 Skip 5 Skip 5 CCR matches before interrupt 5 Skip 6 Skip 6 CCR matches before interrupt 6 Skip 7 Skip 7 CCR matches before interrupt 7 Skip 8 Skip 8 CCR matches before interrupt 8 Skip 9 Skip 9 CCR matches before interrupt 9 CCLATCH CCR Register Latch Mode 5 7 read-write CTR=0/Rising Compare(latch on CTR=0)/ Capture(latch on rising edge) 0 CTR=Period/Falling Compare(latch on CTR=Period)/ Capture(latch on falling edge) 1 Immediate/Both Compare(latch immediately)/ Capture(latch on both edges) 2 CCOUTINV Invert CCR Output 4 5 read-write Not Inverted Do not invert CCR output 0 Inverted Invert CCR output 1 MODE CCR Mode 0 1 read-write Compare Compare Mode 0 Capture Capture Mode 1 CCTL3 Timer D CC Control 3 0x118 32 read-write n 0x0 0x0 CCFORCE Write 1 to force compare event (self-clearing) 7 8 read-write CCINTEDGE Capture Mode Interrupt Edge Setting 2 4 read-write Rising Rising Edge Interrupt 0 Falling Falling Edge Interrupt 1 Both Rising and Falling Edge Interrupt 2 CCINTEN CCR Interrupt Enable 1 2 read-write Disabled CCR interrupt disabled 0 Enabled CCR interrupt enabled 1 CCINTSKIP CC Interrupt Skip Counter 8 12 read-write Don't Skip Don't skip CCR matches before interrupt 0 Skip 1 Skip 1 CCR match before interrupt 1 Skip 10 Skip 10 CCR matches before interrupt 10 Skip 11 Skip 11 CCR matches before interrupt 11 Skip 12 Skip 12 CCR matches before interrupt 12 Skip 13 Skip 13 CCR matches before interrupt 13 Skip 14 Skip 14 CCR matches before interrupt 14 Skip 15 Skip 15 CCR matches before interrupt 15 Skip 2 Skip 2 CCR matches before interrupt 2 Skip 3 Skip 3 CCR matches before interrupt 3 Skip 4 Skip 4 CCR matches before interrupt 4 Skip 5 Skip 5 CCR matches before interrupt 5 Skip 6 Skip 6 CCR matches before interrupt 6 Skip 7 Skip 7 CCR matches before interrupt 7 Skip 8 Skip 8 CCR matches before interrupt 8 Skip 9 Skip 9 CCR matches before interrupt 9 CCLATCH CCR Register Latch Mode 5 7 read-write CTR=0/Rising Compare(latch on CTR=0)/ Capture(latch on rising edge) 0 CTR=Period/Falling Compare(latch on CTR=Period)/ Capture(latch on falling edge) 1 Immediate/Both Compare(latch immediately)/ Capture(latch on both edges) 2 CCOUTINV Invert CCR Output 4 5 read-write Not Inverted Do not invert CCR output 0 Inverted Invert CCR output 1 MODE CCR Mode 0 1 read-write Compare Compare Mode 0 Capture Capture Mode 1 CCTL4 Timer D CC Control 4 0x120 32 read-write n 0x0 0x0 CCFORCE Write 1 to force compare event (self-clearing) 7 8 read-write CCINTEDGE Capture Mode Interrupt Edge Setting 2 4 read-write Rising Rising Edge Interrupt 0 Falling Falling Edge Interrupt 1 Both Rising and Falling Edge Interrupt 2 CCINTEN CCR Interrupt Enable 1 2 read-write Disabled CCR interrupt disabled 0 Enabled CCR interrupt enabled 1 CCINTSKIP CC Interrupt Skip Counter 8 12 read-write Don't Skip Don't skip CCR matches before interrupt 0 Skip 1 Skip 1 CCR match before interrupt 1 Skip 10 Skip 10 CCR matches before interrupt 10 Skip 11 Skip 11 CCR matches before interrupt 11 Skip 12 Skip 12 CCR matches before interrupt 12 Skip 13 Skip 13 CCR matches before interrupt 13 Skip 14 Skip 14 CCR matches before interrupt 14 Skip 15 Skip 15 CCR matches before interrupt 15 Skip 2 Skip 2 CCR matches before interrupt 2 Skip 3 Skip 3 CCR matches before interrupt 3 Skip 4 Skip 4 CCR matches before interrupt 4 Skip 5 Skip 5 CCR matches before interrupt 5 Skip 6 Skip 6 CCR matches before interrupt 6 Skip 7 Skip 7 CCR matches before interrupt 7 Skip 8 Skip 8 CCR matches before interrupt 8 Skip 9 Skip 9 CCR matches before interrupt 9 CCLATCH CCR Register Latch Mode 5 7 read-write CTR=0/Rising Compare(latch on CTR=0)/ Capture(latch on rising edge) 0 CTR=Period/Falling Compare(latch on CTR=Period)/ Capture(latch on falling edge) 1 Immediate/Both Compare(latch immediately)/ Capture(latch on both edges) 2 CCOUTINV Invert CCR Output 4 5 read-write Not Inverted Do not invert CCR output 0 Inverted Invert CCR output 1 MODE CCR Mode 0 1 read-write Compare Compare Mode 0 Capture Capture Mode 1 CCTL5 Timer D CC Control 5 0x128 32 read-write n 0x0 0x0 CCFORCE Write 1 to force compare event (self-clearing) 7 8 read-write CCINTEDGE Capture Mode Interrupt Edge Setting 2 4 read-write Rising Rising Edge Interrupt 0 Falling Falling Edge Interrupt 1 Both Rising and Falling Edge Interrupt 2 CCINTEN CCR Interrupt Enable 1 2 read-write Disabled CCR interrupt disabled 0 Enabled CCR interrupt enabled 1 CCINTSKIP CC Interrupt Skip Counter 8 12 read-write Don't Skip Don't skip CCR matches before interrupt 0 Skip 1 Skip 1 CCR match before interrupt 1 Skip 10 Skip 10 CCR matches before interrupt 10 Skip 11 Skip 11 CCR matches before interrupt 11 Skip 12 Skip 12 CCR matches before interrupt 12 Skip 13 Skip 13 CCR matches before interrupt 13 Skip 14 Skip 14 CCR matches before interrupt 14 Skip 15 Skip 15 CCR matches before interrupt 15 Skip 2 Skip 2 CCR matches before interrupt 2 Skip 3 Skip 3 CCR matches before interrupt 3 Skip 4 Skip 4 CCR matches before interrupt 4 Skip 5 Skip 5 CCR matches before interrupt 5 Skip 6 Skip 6 CCR matches before interrupt 6 Skip 7 Skip 7 CCR matches before interrupt 7 Skip 8 Skip 8 CCR matches before interrupt 8 Skip 9 Skip 9 CCR matches before interrupt 9 CCLATCH CCR Register Latch Mode 5 7 read-write CTR=0/Rising Compare(latch on CTR=0)/ Capture(latch on rising edge) 0 CTR=Period/Falling Compare(latch on CTR=Period)/ Capture(latch on falling edge) 1 Immediate/Both Compare(latch immediately)/ Capture(latch on both edges) 2 CCOUTINV Invert CCR Output 4 5 read-write Not Inverted Do not invert CCR output 0 Inverted Invert CCR output 1 MODE CCR Mode 0 1 read-write Compare Compare Mode 0 Capture Capture Mode 1 CCTL6 Timer D CC Control 6 0x130 32 read-write n 0x0 0x0 CCFORCE Write 1 to force compare event (self-clearing) 7 8 read-write CCINTEDGE Capture Mode Interrupt Edge Setting 2 4 read-write Rising Rising Edge Interrupt 0 Falling Falling Edge Interrupt 1 Both Rising and Falling Edge Interrupt 2 CCINTEN CCR Interrupt Enable 1 2 read-write Disabled CCR interrupt disabled 0 Enabled CCR interrupt enabled 1 CCINTSKIP CC Interrupt Skip Counter 8 12 read-write Don't Skip Don't skip CCR matches before interrupt 0 Skip 1 Skip 1 CCR match before interrupt 1 Skip 10 Skip 10 CCR matches before interrupt 10 Skip 11 Skip 11 CCR matches before interrupt 11 Skip 12 Skip 12 CCR matches before interrupt 12 Skip 13 Skip 13 CCR matches before interrupt 13 Skip 14 Skip 14 CCR matches before interrupt 14 Skip 15 Skip 15 CCR matches before interrupt 15 Skip 2 Skip 2 CCR matches before interrupt 2 Skip 3 Skip 3 CCR matches before interrupt 3 Skip 4 Skip 4 CCR matches before interrupt 4 Skip 5 Skip 5 CCR matches before interrupt 5 Skip 6 Skip 6 CCR matches before interrupt 6 Skip 7 Skip 7 CCR matches before interrupt 7 Skip 8 Skip 8 CCR matches before interrupt 8 Skip 9 Skip 9 CCR matches before interrupt 9 CCLATCH CCR Register Latch Mode 5 7 read-write CTR=0/Rising Compare(latch on CTR=0)/ Capture(latch on rising edge) 0 CTR=Period/Falling Compare(latch on CTR=Period)/ Capture(latch on falling edge) 1 Immediate/Both Compare(latch immediately)/ Capture(latch on both edges) 2 CCOUTINV Invert CCR Output 4 5 read-write Not Inverted Do not invert CCR output 0 Inverted Invert CCR output 1 MODE CCR Mode 0 1 read-write Compare Compare Mode 0 Capture Capture Mode 1 CCTL7 Timer D CC Control 7 0x138 32 read-write n 0x0 0x0 CCFORCE Write 1 to force compare event (self-clearing) 7 8 read-write CCINTEDGE Capture Mode Interrupt Edge Setting 2 4 read-write Rising Rising Edge Interrupt 0 Falling Falling Edge Interrupt 1 Both Rising and Falling Edge Interrupt 2 CCINTEN CCR Interrupt Enable 1 2 read-write Disabled CCR interrupt disabled 0 Enabled CCR interrupt enabled 1 CCINTSKIP CC Interrupt Skip Counter 8 12 read-write Don't Skip Don't skip CCR matches before interrupt 0 Skip 1 Skip 1 CCR match before interrupt 1 Skip 10 Skip 10 CCR matches before interrupt 10 Skip 11 Skip 11 CCR matches before interrupt 11 Skip 12 Skip 12 CCR matches before interrupt 12 Skip 13 Skip 13 CCR matches before interrupt 13 Skip 14 Skip 14 CCR matches before interrupt 14 Skip 15 Skip 15 CCR matches before interrupt 15 Skip 2 Skip 2 CCR matches before interrupt 2 Skip 3 Skip 3 CCR matches before interrupt 3 Skip 4 Skip 4 CCR matches before interrupt 4 Skip 5 Skip 5 CCR matches before interrupt 5 Skip 6 Skip 6 CCR matches before interrupt 6 Skip 7 Skip 7 CCR matches before interrupt 7 Skip 8 Skip 8 CCR matches before interrupt 8 Skip 9 Skip 9 CCR matches before interrupt 9 CCLATCH CCR Register Latch Mode 5 7 read-write CTR=0/Rising Compare(latch on CTR=0)/ Capture(latch on rising edge) 0 CTR=Period/Falling Compare(latch on CTR=Period)/ Capture(latch on falling edge) 1 Immediate/Both Compare(latch immediately)/ Capture(latch on both edges) 2 CCOUTINV Invert CCR Output 4 5 read-write Not Inverted Do not invert CCR output 0 Inverted Invert CCR output 1 MODE CCR Mode 0 1 read-write Compare Compare Mode 0 Capture Capture Mode 1 CCTR0 Timer D CC Counter 0 0x104 read-write n 0x0 0x0 CCTR1 Timer D CC Counter 1 0x10C read-write n 0x0 0x0 CCTR2 Timer D CC Counter 2 0x114 read-write n 0x0 0x0 CCTR3 Timer D CC Counter 3 0x11C read-write n 0x0 0x0 CCTR4 Timer D CC Counter 4 0x124 read-write n 0x0 0x0 CCTR5 Timer D CC Counter 5 0x12C read-write n 0x0 0x0 CCTR6 Timer D CC Counter 6 0x134 read-write n 0x0 0x0 CCTR7 Timer D CC Counter 7 0x13C read-write n 0x0 0x0 CTL Timer D Control 0x0 32 read-write n 0x0 0x0 BASEIE Base timer interrupt enable 13 14 read-write Disabled Base interrupt disabled 0 Enabled Base interrupt enabled 1 CLKDIV Timer Input Clock Divider 6 9 read-write /1 Timer input clock /1 0 /2 Timer input clock /2 1 /4 Timer input clock /4 2 /8 Timer input clock /8 3 /16 Timer input clock /16 4 /32 Timer input clock /32 5 /64 Timer input clock /64 6 /128 Timer input clock /128 7 CLKSRC Timer Clock Source 9 10 read-write PCLK PCLK selected as input to timer 0 ACLK ACLK selected as input to timer 1 CLR Timer Clear 12 13 read-write Do Not Clear Do not clear timer counter 0 Clear Clear timer counter 1 DTGCLK Dead-Time Generator Clock Source 10 11 read-write Before Divider Before input clock divider 0 After Divider After input clock divider 1 LATCH Write 1 to Latch Period and all CCTRs 11 12 read-write MODE Timer Mode 0 2 read-write Disabled Disabled Mode 0 Up Up Mode 1 Up/Down Up/Down Mode 2 Asymmetric Asymmetric Mode 3 PRDLATCH Timer Period Latch Mode 2 4 read-write CTR=0 Period is latched when CTR = 0 0 CTR=Period Period is latched when CTR = Period 1 Immediate Period is latched immediately upon register write 2 SINGLE Single Shot Timer 5 6 read-write Disabled Single Shot Disabled (auto-reload) 0 Enabled Single Shot Timer Enabled 1 SSYNC Timer Slave Synchronization 4 5 read-write Disabled Slave Sync Disabled 0 Enabled Slave Sync Enabled 1 CTR Timer D Counter 0xC read-write n 0x0 0x0 DTGCTL0 Timer D DTG Control 0 0x200 read-write n 0x0 0x0 DTGCTL1 Timer D DTG Control 1 0x204 read-write n 0x0 0x0 DTGCTL2 Timer D DTG Control 2 0x208 read-write n 0x0 0x0 DTGCTL3 Timer D DTG Control 3 0x20C read-write n 0x0 0x0 INT Timer D Interrupt Control 0x4 read-write n 0x0 0x0 PRD Timer D Period 0x8 read-write n 0x0 0x0 QEPCTL Timer D QEP Control 0x10 read-write n 0x0 0x0 USARTA USART A USARTA 0x0 0x0 0x10000 registers n USARTA USART A Interrupt 23 DRL_DAT UART A Divisor Latch / SSP A Data 0x8 read-write n 0x0 0x0 EFR Enhanced Feature 0x2C read-write n 0x0 0x0 FCR_RIS UART A FIFO Control / SSP A Raw Interrupt Status 0x14 read-write n 0x0 0x0 ICLR SSP A Interrupt Clear 0x1C read-write n 0x0 0x0 IER_CLK UART A Interrupt Enable / SSP A Clock Control 0xC read-write n 0x0 0x0 IIR_IMSC UART A Interrupt Identification / SSP A Interrupt Mask Set and Clear 0x10 read-write n 0x0 0x0 LCR_MIS UART A Line Control / SSP A Masked Interrupt Status 0x18 read-write n 0x0 0x0 LSR UART A Line Status 0x20 read-write n 0x0 0x0 RBR_CON UART A Receive Buffer / SSP A Control 0x0 read-write n 0x0 0x0 SCR_SSCR UART A Scratch Pad / SSP A Slave Select Configuration 0x28 read-write n 0x0 0x0 THR_STAT UART A Transmit Holding / SSP A Status 0x4 read-write n 0x0 0x0 USARTB USART B USARTB 0x0 0x0 0x10000 registers n USARTB USART B Interrupt 24 DRL_DAT UART B Divisor Latch / SSP B Data 0x8 read-write n 0x0 0x0 EFR Enhanced Feature 0x2C read-write n 0x0 0x0 FCR_RIS UART B FIFO Control / SSP B Raw Interrupt Status 0x14 read-write n 0x0 0x0 ICLR SSP B Interrupt Clear 0x1C read-write n 0x0 0x0 IER_CLK UART B Interrupt Enable / SSP B Clock Control 0xC read-write n 0x0 0x0 IIR_IMSC UART B Interrupt Identification / SSP B Interrupt Mask Set and Clear 0x10 read-write n 0x0 0x0 LCR_MIS UART B Line Control / SSP B Masked Interrupt Status 0x18 read-write n 0x0 0x0 LSR UART B Line Status 0x20 read-write n 0x0 0x0 RBR_CON UART B Receive Buffer / SSP B Control 0x0 read-write n 0x0 0x0 SCR_SSCR UART B Scratch Pad / SSP B Slave Select Configuration 0x28 read-write n 0x0 0x0 THR_STAT UART B Transmit Holding / SSP B Status 0x4 read-write n 0x0 0x0 USARTC USART C USARTC 0x0 0x0 0x10000 registers n USARTC USART C Interrupt 25 DRL_DAT UART C Divisor Latch / SSP C Data 0x8 read-write n 0x0 0x0 EFR Enhanced Feature 0x2C read-write n 0x0 0x0 FCR_RIS UART C FIFO Control / SSP C Raw Interrupt Status 0x14 read-write n 0x0 0x0 ICLR SSP C Interrupt Clear 0x1C read-write n 0x0 0x0 IER_CLK UART C Interrupt Enable / SSP C Clock Control 0xC read-write n 0x0 0x0 IIR_IMSC UART C Interrupt Identification / SSP C Interrupt Mask Set and Clear 0x10 read-write n 0x0 0x0 LCR_MIS UART C Line Control / SSP C Masked Interrupt Status 0x18 read-write n 0x0 0x0 LSR UART C Line Status 0x20 read-write n 0x0 0x0 RBR_CON UART C Receive Buffer / SSP C Control 0x0 read-write n 0x0 0x0 SCR_SSCR UART C Scratch Pad / SSP C Slave Select Configuration 0x28 read-write n 0x0 0x0 THR_STAT UART C Transmit Holding / SSP C Status 0x4 read-write n 0x0 0x0 USARTD USART D USARTD 0x0 0x0 0x10000 registers n USARTD USART D Interrupt 26 DRL_DAT UART D Divisor Latch / SSP D Data 0x8 read-write n 0x0 0x0 EFR Enhanced Feature 0x2C read-write n 0x0 0x0 FCR_RIS UART D FIFO Control / SSP D Raw Interrupt Status 0x14 read-write n 0x0 0x0 ICLR SSP D Interrupt Clear 0x1C read-write n 0x0 0x0 IER_CLK UART D Interrupt Enable / SSP D Clock Control 0xC read-write n 0x0 0x0 IIR_IMSC UART D Interrupt Identification / SSP D Interrupt Mask Set and Clear 0x10 read-write n 0x0 0x0 LCR_MIS UART D Line Control / SSP D Masked Interrupt Status 0x18 read-write n 0x0 0x0 LSR UART D Line Status 0x20 read-write n 0x0 0x0 RBR_CON UART D Receive Buffer / SSP D Control 0x0 read-write n 0x0 0x0 SCR_SSCR UART D Scratch Pad / SSP D Slave Select Configuration 0x28 read-write n 0x0 0x0 THR_STAT UART D Transmit Holding / SSP D Status 0x4 read-write n 0x0 0x0 WWDT Windowed Watchdog Timer WWDT 0x0 0x0 0x400 registers n WWDT WWDT Interrupt 1 CTL WWDT Control 0x0 read-write n 0x0 0x0 CTR WWDT Counter 0x8 read-write n 0x0 0x0 INTCLR WWDT Interrupt Clear 0x10 read-write n 0x0 0x0 INTF WWDT Interrupt Flag 0xC read-write n 0x0 0x0 LOAD WWDT Load Counter Value 0x4 read-write n 0x0 0x0 LOCK WWDT Lock 0x14 read-write n 0x0 0x0