silan SC32F5364 2025.11.04 SC32F5364 M0 CM0 r0p0 little 2 false 8 32 ACMPOPA ACMPOPA ACMPOPA 0x400AA000 0x0 0x80 registers n ACMPOPA ACMP_OPA Interrupt 5 CP0CFG CP0CFG Register 0x4 32 read-write n 0x100 0xFFFFFFFF C0CLKD C0CLKD 12 5 read-write C0DFILT C0DFILT 20 10 read-write C0FLG C0FLG 11 1 read-write C0FRO C0FRO 2 1 read-only C0GCEN C0GCEN 3 1 read-write C0GCS C0GCS 4 4 read-write C0INTM C0INTM 8 1 read-write C0INTS C0INTS 9 2 read-write C0OINV C0OINV 0 1 read-write C0RO C0RO 1 1 read-only CP0CON CP0CON Register 0x0 32 read-write n 0x0 0xFFFFFFFF C0AFILT C0AFILT 22 1 read-write C0EN C0EN 20 1 read-write C0HYSEN C0HYSEN 8 1 read-write C0NIOS C0NIOS 26 2 read-write C0NS C0NS 4 2 read-write C0PIOS C0PIOS 24 2 read-write C0PS C0PS 0 2 read-write C0RDS C0RDS 15 5 read-write C0REFEN C0REFEN 11 1 read-write C0REFOES C0REFOES 28 1 read-write C0VRHS C0VRHS 12 1 read-write C0VRRH C0VRRH 13 1 read-write C0VRRL C0VRRL 14 1 read-write OPACON OP0_CFG Register 0x40 32 read-write n 0x0 0xFFFFFFFF OPBES OPBES 24 1 read-write OPBS OPBS 25 1 read-write OPEN OPEN 0 1 read-write OPNS OPNS 4 1 read-write OPOE OPOE 12 1 read-write OPOSTRIM OPOSTRIM 20 4 read-write OPPS OPPS 2 1 read-write OPRSEL OPRSEL 16 4 read-write RNSHT RNSHT 9 1 read-write RPSHT RPSHT 8 1 read-write ADC ADC ADC 0x400A8000 0x0 0x240 registers n ADC_SEQA ADC_SEQA Interrupt 12 ADC ADC Interrupt 22 ADC_SEQB ADC_SEQB Interrupt 27 ADCCTRL ADC Control 0x0 32 read-write n 0x7000 0xFFFFFFFF ADC_CLKON ADC_CLKON Bit 8 1 read-write CLKDIV ADC CLKDIV Bit 0 8 read-write EXRF_SEL EXRF_SEL 15 1 read-write PD_ADC PD_ADC Control Bit 14 1 read-write PD_ADC_CORE PD_ADC_CORE 13 1 read-write PD_ADC_REF PD_ADC_REF Bit 12 1 read-write SEQA_LOWPRIO SEQA_LOWPRIO Control Bit 16 1 read-write CHL_THRSEL CHL_THRSEL_REG 0x68 32 read-write n 0x0 0xFFFFFFFF CHL_THRSEL CHL_THRSEL Bit 0 16 read-write CMPFLAG CMPFLAG_REG Flag 0x74 32 read-write n 0x0 0xFFFFFFFF OVERRUN0 OVERRUN0 16 1 read-only OVERRUN1 OVERRUN1 17 1 read-only OVERRUN10 OVERRUN10 26 1 read-only OVERRUN11 OVERRUN11 27 1 read-only OVERRUN12 OVERRUN12 28 1 read-only OVERRUN13 OVERRUN13 29 1 read-only OVERRUN14 OVERRUN14 30 1 read-only OVERRUN15 OVERRUN15 31 1 read-only OVERRUN2 OVERRUN2 18 1 read-only OVERRUN3 OVERRUN3 19 1 read-only OVERRUN4 OVERRUN4 20 1 read-only OVERRUN5 OVERRUN5 21 1 read-only OVERRUN6 OVERRUN6 22 1 read-only OVERRUN7 OVERRUN7 23 1 read-only OVERRUN8 OVERRUN8 24 1 read-only OVERRUN9 OVERRUN9 25 1 read-only THCMP0 THCMP0 0 1 read-write THCMP1 THCMP1 1 1 read-write THCMP10 THCMP10 10 1 read-write THCMP11 THCMP11 11 1 read-write THCMP12 THCMP12 12 1 read-write THCMP13 THCMP13 13 1 read-write THCMP14 THCMP14 14 1 read-write THCMP15 THCMP15 15 1 read-write THCMP2 THCMP2 2 1 read-write THCMP3 THCMP3 3 1 read-write THCMP4 THCMP4 4 1 read-write THCMP5 THCMP5 5 1 read-write THCMP6 THCMP6 6 1 read-write THCMP7 THCMP7 7 1 read-write THCMP8 THCMP8 8 1 read-write THCMP9 THCMP9 9 1 read-write CMPINTEN CMPINTEN_REG 0x6C 32 read-write n 0x0 0xFFFFFFFF CHL0_CMPINTEN CHL0_CMPINTEN Bit 0 2 read-write CHL10_CMPINTEN CHL10_CMPINTEN Bit 20 2 read-write CHL11_CMPINTEN CHL11_CMPINTEN Bit 22 2 read-write CHL12_CMPINTEN CHL12_CMPINTEN Bit 24 2 read-write CHL13_CMPINTEN CHL13_CMPINTEN Bit 26 2 read-write CHL14_CMPINTEN CHL14_CMPINTEN Bit 28 2 read-write CHL15_CMPINTEN CHL15_CMPINTEN Bit 30 2 read-write CHL1_CMPINTEN CHL1_CMPINTEN Bit 2 2 read-write CHL2_CMPINTEN CHL2_CMPINTEN Bit 4 2 read-write CHL3_CMPINTEN CHL3_CMPINTEN Bit 6 2 read-write CHL4_CMPINTEN CHL4_CMPINTEN Bit 8 2 read-write CHL5_CMPINTEN CHL5_CMPINTEN Bit 10 2 read-write CHL6_CMPINTEN CHL6_CMPINTEN Bit 12 2 read-write CHL7_CMPINTEN CHL7_CMPINTEN Bit 14 2 read-write CHL8_CMPINTEN CHL8_CMPINTEN Bit 16 2 read-write CHL9_CMPINTEN CHL9_CMPINTEN Bit 18 2 read-write DAT0 DATA result register 0x20 32 read-only n 0x0 0xFFFFFFFF CHN CHN 24 4 read-only DATAVALID DATAVALID Bit 29 1 read-only OVERRUN OVERRUN Bit 28 1 read-only RESULT RESULT Bit 0 12 read-only THCMPCROSS THCMPCROSS Bit 18 2 read-only THCMPRANGE THCMPRANGE 16 2 read-only DAT1 DATA result register 0x24 32 read-only n 0x0 0xFFFFFFFF CHN CHN 24 4 read-only DATAVALID DATAVALID Bit 29 1 read-only OVERRUN OVERRUN Bit 28 1 read-only RESULT RESULT Bit 0 12 read-only THCMPCROSS THCMPCROSS Bit 18 2 read-only THCMPRANGE THCMPRANGE 16 2 read-only DAT10 DATA result register 0x48 32 read-only n 0x0 0xFFFFFFFF CHN CHN 24 4 read-only DATAVALID DATAVALID Bit 29 1 read-only OVERRUN OVERRUN Bit 28 1 read-only RESULT RESULT Bit 0 12 read-only THCMPCROSS THCMPCROSS Bit 18 2 read-only THCMPRANGE THCMPRANGE 16 2 read-only DAT11 DATA result register 0x4C 32 read-only n 0x0 0xFFFFFFFF CHN CHN 24 4 read-only DATAVALID DATAVALID Bit 29 1 read-only OVERRUN OVERRUN Bit 28 1 read-only RESULT RESULT Bit 0 12 read-only THCMPCROSS THCMPCROSS Bit 18 2 read-only THCMPRANGE THCMPRANGE 16 2 read-only DAT12 DATA result register 0x50 32 read-only n 0x0 0xFFFFFFFF CHN CHN 24 4 read-only DATAVALID DATAVALID Bit 29 1 read-only OVERRUN OVERRUN Bit 28 1 read-only RESULT RESULT Bit 0 12 read-only THCMPCROSS THCMPCROSS Bit 18 2 read-only THCMPRANGE THCMPRANGE 16 2 read-only DAT13 DATA result register 0x54 32 read-only n 0x0 0xFFFFFFFF CHN CHN 24 4 read-only DATAVALID DATAVALID Bit 29 1 read-only OVERRUN OVERRUN Bit 28 1 read-only RESULT RESULT Bit 0 12 read-only THCMPCROSS THCMPCROSS Bit 18 2 read-only THCMPRANGE THCMPRANGE 16 2 read-only DAT14 DATA result register 0x58 32 read-only n 0x0 0xFFFFFFFF CHN CHN 24 4 read-only DATAVALID DATAVALID Bit 29 1 read-only OVERRUN OVERRUN Bit 28 1 read-only RESULT RESULT Bit 0 12 read-only THCMPCROSS THCMPCROSS Bit 18 2 read-only THCMPRANGE THCMPRANGE 16 2 read-only DAT15 DATA result register 0x5C 32 read-only n 0x0 0xFFFFFFFF CHN CHN 24 4 read-only DATAVALID DATAVALID Bit 29 1 read-only OVERRUN OVERRUN Bit 28 1 read-only RESULT RESULT Bit 0 12 read-only THCMPCROSS THCMPCROSS Bit 18 2 read-only THCMPRANGE THCMPRANGE 16 2 read-only DAT2 DATA result register 0x28 32 read-only n 0x0 0xFFFFFFFF CHN CHN 24 4 read-only DATAVALID DATAVALID Bit 29 1 read-only OVERRUN OVERRUN Bit 28 1 read-only RESULT RESULT Bit 0 12 read-only THCMPCROSS THCMPCROSS Bit 18 2 read-only THCMPRANGE THCMPRANGE 16 2 read-only DAT3 DATA result register 0x2C 32 read-only n 0x0 0xFFFFFFFF CHN CHN 24 4 read-only DATAVALID DATAVALID Bit 29 1 read-only OVERRUN OVERRUN Bit 28 1 read-only RESULT RESULT Bit 0 12 read-only THCMPCROSS THCMPCROSS Bit 18 2 read-only THCMPRANGE THCMPRANGE 16 2 read-only DAT4 DATA result register 0x30 32 read-only n 0x0 0xFFFFFFFF CHN CHN 24 4 read-only DATAVALID DATAVALID Bit 29 1 read-only OVERRUN OVERRUN Bit 28 1 read-only RESULT RESULT Bit 0 12 read-only THCMPCROSS THCMPCROSS Bit 18 2 read-only THCMPRANGE THCMPRANGE 16 2 read-only DAT5 DATA result register 0x34 32 read-only n 0x0 0xFFFFFFFF CHN CHN 24 4 read-only DATAVALID DATAVALID Bit 29 1 read-only OVERRUN OVERRUN Bit 28 1 read-only RESULT RESULT Bit 0 12 read-only THCMPCROSS THCMPCROSS Bit 18 2 read-only THCMPRANGE THCMPRANGE 16 2 read-only DAT6 DATA result register 0x38 32 read-only n 0x0 0xFFFFFFFF CHN CHN 24 4 read-only DATAVALID DATAVALID Bit 29 1 read-only OVERRUN OVERRUN Bit 28 1 read-only RESULT RESULT Bit 0 12 read-only THCMPCROSS THCMPCROSS Bit 18 2 read-only THCMPRANGE THCMPRANGE 16 2 read-only DAT7 DATA result register 0x3C 32 read-only n 0x0 0xFFFFFFFF CHN CHN 24 4 read-only DATAVALID DATAVALID Bit 29 1 read-only OVERRUN OVERRUN Bit 28 1 read-only RESULT RESULT Bit 0 12 read-only THCMPCROSS THCMPCROSS Bit 18 2 read-only THCMPRANGE THCMPRANGE 16 2 read-only DAT8 DATA result register 0x40 32 read-only n 0x0 0xFFFFFFFF CHN CHN 24 4 read-only DATAVALID DATAVALID Bit 29 1 read-only OVERRUN OVERRUN Bit 28 1 read-only RESULT RESULT Bit 0 12 read-only THCMPCROSS THCMPCROSS Bit 18 2 read-only THCMPRANGE THCMPRANGE 16 2 read-only DAT9 DATA result register 0x44 32 read-only n 0x0 0xFFFFFFFF CHN CHN 24 4 read-only DATAVALID DATAVALID Bit 29 1 read-only OVERRUN OVERRUN Bit 28 1 read-only RESULT RESULT Bit 0 12 read-only THCMPCROSS THCMPCROSS Bit 18 2 read-only THCMPRANGE THCMPRANGE 16 2 read-only FLAG ADC_FLAGS_REG 0x78 32 read-write n 0x0 0xFFFFFFFF ADC_OVR_FLAG ADC_OVR_FLAG Bit 2 1 read-write ADC_THCMP_FLAG ADC_THCMP_FLAG 3 1 read-write SEQA_FLAG SEQA_FLAG Bit 0 1 read-write SEQA_OVR_FLAG SEQA_OVR_FLAG Bit 4 1 read-write SEQB_FLAG SEQB_FLAG 1 1 read-write SEQB_OVR_FLAG SEQB_OVR_FLAG Bit 5 1 read-write INTEN ADC_INTEN_REG 0x70 32 read-write n 0x0 0xFFFFFFFF ADC_OVR_INTEN ADC_OVR_INTEN Bit 2 1 read-write ADC_THRCMP_INTEN ADC_THRCMP_INTEN Bit 3 1 read-write SEQA_INTEN SEQA_INTEN Bit 0 1 read-write SEQA_OVR_INTEN SEQA_OVR_INTEN Bit 4 1 read-write SEQB_INTEN SEQB_INTEN Bit 1 1 read-write SEQB_OVR_INTEN SEQB_OVR_INTEN Bit 5 1 read-write SEQA_CTRL SEQA_CTRL_REG 0x4 32 read-write n 0x0 0xFFFFFFFF SEQA_BURST SEQA_BURST Bit 25 1 read-write SEQA_CH_SEL SEQA_CH_SEL Bit 0 16 read-write SEQA_EN SEQA_EN Bit 29 1 read-write SEQA_MODE SEQA_MODE Bit 28 1 read-write SEQA_SSTEP SEQA_SSTEP Bit 26 1 read-write SEQA_START SEQA_START Bit 24 1 read-write SEQA_SYNCBYP SEQA_SYNCBYP 21 1 read-write SEQA_TRIGPOL SEQA_TRIGPOL Bit 20 1 read-write SEQA_TRIGSEL SEQA_TRIGSEL 16 4 read-write SEQA_GDAT SEQA_GDAT_REG 0x14 32 read-write n 0x0 0xFFFFFFFF CHN CHN 24 4 read-only DATAVALID DATAVALID Bit 29 1 read-only OVERRUN OVERRUN Bit 28 1 read-only RESULT RESULT Bit 0 12 read-only THCMPCROSS THCMPCROSS Bit 18 2 read-only THCMPRANGE THCMPRANGE 16 2 read-only SEQA_PERD SEQA_PERD 0xC 32 read-write n 0x80 0xFFFFFFFF SEQB_CTRL SEQB_CTRL_REG 0x8 32 read-write n 0x0 0xFFFFFFFF SEQB_BURST SEQB_BURST Bit 25 1 read-write SEQB_CH_SEL SEQB_CH_SEL Bit 0 16 read-write SEQB_EN SEQB_EN Bit 29 1 read-write SEQB_MODE SEQB_MODE Bit 28 1 read-write SEQB_SSTEP SEQB_SSTEP Bit 26 1 read-write SEQB_START SEQB_START Bit 24 1 read-write SEQB_SYNCBYP SEQB_SYNCBYP 21 1 read-write SEQB_TRIGPOL SEQB_TRIGPOL Bit 20 1 read-write SEQB_TRIGSEL SEQB_TRIGSEL 16 4 read-write SEQB_GDAT SEQB_GDAT_REG 0x18 32 read-write n 0x0 0xFFFFFFFF CHN CHN 24 4 read-only DATAVALID DATAVALID Bit 29 1 read-only OVERRUN OVERRUN Bit 28 1 read-only RESULT RESULT Bit 0 12 read-only THCMPCROSS THCMPCROSS Bit 18 2 read-only THCMPRANGE THCMPRANGE 16 2 read-only SEQB_PERD SEQB_PERD 0x10 32 read-write n 0x80 0xFFFFFFFF THR0 ADC_THR0_REG 0x60 32 read-write n 0xFFFF0000 0xFFFFFFFF THR0_HIGH THR0_HIGH 16 12 read-write THR0_LOW THR0_LOW Bit 0 12 read-write THR1 ADC_THR1_REG 0x64 32 read-write n 0xFFFF0000 0xFFFFFFFF THR1_HIGH THR1_HIGH 16 12 read-write THR1_LOW THR1_LOW Bit 0 12 read-write TRIM ADC_TRIM_REG Register 0x7C 32 read-write n 0x0 0xFFFFFFFF ADC_I25UT_OE ADC_I25UT_OE 16 1 read-write ADC_INB6_SEL ADC_INB6_SEL 20 1 read-write ADC_INB7_SEL ADC_INB7_SEL 21 1 read-write ADC_VBG_OE ADC_VBG_OE 17 1 read-write ADC_VREFLI_TIE ADC_VREFLI_TIE 18 1 read-write R10B R10B 31 1 read-write TRIM_GAIN TRIM_GAIN 8 8 read-write TRIM_MEAS TRIM_MEAS 28 1 read-write VFS_S VFS_S 0 2 read-write CHIPCTL CHIPCTL CHIPCTL 0x40081000 0x0 0xC04 registers n IWDT IWDT Interrupt 15 WT WT Interrupt 20 CHIP_KEY CHIP_KEY Register 0x800 32 read-write n 0x0 0xFFFFFFFF KEY KEY 0 32 read-write CLKCFG0 CLKCFG0 Register 0x4 32 read-write n 0x0 0xFFFFFFFF PLLDIV PLLDIV 4 4 read-write PLLMUL PLLMUL 10 2 read-write PLLSRC PLLSRC 0 1 read-write XCLKDIV XCLKDIV 28 3 read-write XCLKINSEL XCLKINSEL 20 2 read-write XCLKSEL XCLKSEL 24 4 read-write CLKCFG1 CLKCFG1 Register 0x8 32 read-write n 0x1 0xFFFFFFFF CLK32KSEL CLK32KSEL 2 1 read-write IWRCLKSEL IWRCLKSEL 12 1 read-write LEDCLKSEL LEDCLKSEL 16 1 read-write SYSCLKLOCK SYSCLKLOCK 4 1 read-only SYSCLKSEL SYSCLKSEL 0 2 read-write SYSTICKSEL SYSTICKSEL 8 2 read-write CLKCFG2 CLKCFG2 Register 0xC 32 read-write n 0x1 0xFFFFFFFF HDIV HDIV 0 8 read-write MTDIV MTDIV 8 4 read-write PDIV01 PDIV01 16 4 read-write PDIV23 PDIV23 24 4 read-write CLKCTRL CLKCTRL Register 0x0 32 read-write n 0x2FF1000 0xFFFFFFFF OSCDEN OSCDEN 1 1 read-write OSCEN OSCEN 0 1 read-write OSCGAIN OSCGAIN 4 2 read-write OSCOIEN OSCOIEN 7 1 read-write OSCREN OSCREN 6 1 read-write OSCSTB OSCSTB 11 1 read-only OSCSTOP OSCSTOP 2 1 read-only OSCSTS OSCSTS 8 2 read-write PLLEN PLLEN 28 1 read-write PLLLOCK PLLLOCK 30 1 read-only RCHEN RCHEN 12 1 read-write RCHPT RCHPT 24 4 read-write RCHSTB RCHSTB 14 1 read-only RCHTRIM RCHTRIM 16 8 read-write CLKEN_H01 CLKEN_H01 Register 0x10 32 read-write n 0x27 0xFFFFFFFF PA_CLKEN PA_CLKEN 0 1 read-write PB_CLKEN PB_CLKEN 1 1 read-write PC_CLKEN PC_CLKEN 2 1 read-write PF_CLKEN PF_CLKEN 5 1 read-write CLKEN_H23 CLKEN_H23 Register 0x14 32 read-write n 0x0 0xFFFFFFFF CRC_CLKEN CRC_CLKEN 0 1 read-write CLKEN_P01 CLKEN_P01 Register 0x18 32 read-write n 0x0 0xFFFFFFFF DMA_CLKEN DMA_CLKEN 6 1 read-write ERU_CLKEN ERU_CLKEN 3 1 read-write I2C_CLKEN I2C_CLKEN 23 1 read-write PPU_CLKEN PPU_CLKEN 2 1 read-write SSP_CLKEN SSP_CLKEN 24 1 read-write UART1_CLKEN UART1_CLKEN 16 1 read-write UART2_CLKEN UART2_CLKEN 17 1 read-write UART3_CLKEN UART3_CLKEN 18 1 read-write UART4_CLKEN UART4_CLKEN 19 1 read-write UART5_CLKEN UART5_CLKEN 20 1 read-write UART6_CLKEN UART6_CLKEN 21 1 read-write CLKEN_P23 CLKEN_P23 Register 0x1C 32 read-write n 0x0 0xFFFFFFFF ACMP_OPA_CLKEN ACMP_OPA_CLKEN 10 1 read-write ADC_CLKEN ADC_CLKEN 8 1 read-write TIM14_CLKEN TIM14_CLKEN 0 1 read-write TIM15_CLKEN TIM15_CLKEN 1 1 read-write TIM16_CLKEN TIM16_CLKEN 2 1 read-write TIM17_CLKEN TIM17_CLKEN 3 1 read-write TIM1_CLKEN TIM1_CLKEN 12 1 read-write TIM3_CLKEN TIM3_CLKEN 13 1 read-write INTMASK INTMASK Register 0x100 32 read-write n 0xFFFFFFFF 0xFFFFFFFF CVM_MASK CVM_MASK 2 1 read-write DEBUG_VALID_MASK DEBUG_VALID_MASK 12 1 read-write IO_WAKEUP_MASK IO_WAKEUP_MASK 11 1 read-write IWDTRST_MASK IWDTRST_MASK 7 1 read-write LOCKUP_MASK LOCKUP_MASK 9 1 read-write LVD_MASK LVD_MASK 4 1 read-write LVR_MASK LVR_MASK 3 1 read-write NRST_MASK NRST_MASK 5 1 read-write OSCEN_CFGERR_MASK OSCEN_CFGERR_MASK 28 1 read-write OSC_MISS_MASK OSC_MISS_MASK 18 1 read-write PLLEN_CFGERR_MASK PLLEN_CFGERR_MASK 29 1 read-write PLLSRC_CFGERR_MASK PLLSRC_CFGERR_MASK 25 1 read-write PLL_MISS_MASK PLL_MISS_MASK 20 1 read-write POC_MASK POC_MASK 1 1 read-write POR_MASK POR_MASK 0 1 read-write RCHEN_CFGERR_MASK RCHEN_CFGERR_MASK 27 1 read-write RCH_MISS_MASK RCH_MISS_MASK 16 1 read-write SCLKSEL_CFGERR_MASK SCLKSEL_CFGERR_MASK 24 1 read-write SRST_MASK SRST_MASK 8 1 read-write SYSCLKMUX_ERR_MASK SYSCLKMUX_ERR_MASK 22 1 read-write SYSCLKMUX_RST_MASK SYSCLKMUX_RST_MASK 10 1 read-write WDTRST_MASK WDTRST_MASK 6 1 read-write IWDT_CFG IWDT_CFG Register 0x44 32 read-write n 0x0 0xFFFFFFFF WINEN WINEN 0 1 read-write WINSEL WINSEL 8 1 read-write IWDT_CLKDIV IWDT_CLKDIV Register 0x48 32 read-write n 0x0 0xFFFFFFFF CLKDIV CLKDIV 0 4 read-write IWDT_CTRL IWDT_CTRL Register 0x40 32 write-only n 0x0 0xFFFFFFFF CONTROL CONTROL 0 32 write-only IWDT_RLD IWDT_RLD Register 0x4C 32 read-write n 0xFFFF 0xFFFFFFFF RLD RLD 0 16 read-write IWDT_STATUS IWDT_STATUS Register 0x50 32 read-only n 0x0 0xFFFFFFFF CNT CNT 0 16 read-only INTR INTR 16 1 read-only UPDATING UPDATING 31 1 read-only OSC32K_CTRL OSC32K_CTRL Register 0x34 32 read-write n 0x54 0xFFFFFFFF DETEN DETEN 4 1 read-write EN EN 0 1 read-write FAST FAST 10 1 read-write FILEN FILEN 6 1 read-write GAIN GAIN 12 2 read-write INVEN INVEN 8 1 read-write OSCDET OSCDET 16 1 read-only REFEN REFEN 2 1 read-write POWER_CTRL POWER_CTRL Register 0x30 32 read-write n 0x9008 0xFFFFFFFF CVMEN CVMEN 19 1 read-write CVMREN CVMREN 9 1 read-write DEBUG_NOSLEEP DEBUG_NOSLEEP 3 1 read-write FLASH_CG FLASH_CG 4 1 read-write FLASH_LP FLASH_LP 5 1 read-write LOCKUPREN LOCKUPREN 10 1 read-write LPE LPE 0 1 read-write LVDEN LVDEN 20 1 read-write LVES LVES 21 1 read-write LVLS LVLS 22 3 read-write LVREN LVREN 15 1 read-write LVRS LVRS 16 2 read-write MVRPS MVRPS 12 1 read-write MVRSEL MVRSEL 13 1 read-write POCREN POCREN 8 1 read-write SRAM_CG SRAM_CG 6 1 read-write SYSCLK_DCTEN SYSCLK_DCTEN 2 1 read-write SYSCLK_MUX_RSTEN SYSCLK_MUX_RSTEN 1 1 read-write VTSEL VTSEL 28 2 read-write VTSEN VTSEN 27 1 read-write REMAP_CTRL REMAP_CTRL Register 0x3C 32 read-write n 0x1 0xFFFFFFFF DEBUG_USEASFUNC DEBUG_USEASFUNC 12 1 read-write REMAP REMAP 0 1 read-write REMAP_KEY REMAP_KEY 16 16 write-only SYSRESET_OUTEN SYSRESET_OUTEN 9 1 read-write SYSRESET_OUTSEL SYSRESET_OUTSEL 10 1 read-write XRST_USEASFUNC XRST_USEASFUNC 8 1 read-write SRST_REQ_H01 SRST_REQ_H01 Register 0x20 32 read-write n 0xFFFFFFFF 0xFFFFFFFF PA_SRST_REQ PA_SRST_REQ 0 1 read-write PB_SRST_REQ PB_SRST_REQ 1 1 read-write PC_SRST_REQ PC_SRST_REQ 2 1 read-write PF_SRST_REQ PF_SRST_REQ 5 1 read-write SRST_REQ_H23 SRST_REQ_H23 Register 0x24 32 read-write n 0xFFFFFFFF 0xFFFFFFFF CRC_SRST_REQ CRC_SRST_REQ 0 1 read-write SRST_REQ_P01 SRST_REQ_P01 Register 0x28 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DMA_SRST_REQ DMA_SRST_REQ 6 1 read-write ERU_SRST_REQ ERU_SRST_REQ 3 1 read-write I2C_SRST_REQ I2C_SRST_REQ 23 1 read-write PPU_SRST_REQ PPU_SRST_REQ 2 1 read-write SSP_SRST_REQ SSP_SRST_REQ 24 1 read-write UART1_SRST_REQ UART1_SRST_REQ 16 1 read-write UART2_SRST_REQ UART2_SRST_REQ 17 1 read-write UART3_SRST_REQ UART3_SRST_REQ 18 1 read-write UART4_SRST_REQ UART4_SRST_REQ 19 1 read-write UART5_SRST_REQ UART5_SRST_REQ 20 1 read-write UART6_SRST_REQ UART6_SRST_REQ 21 1 read-write SRST_REQ_P23 SRST_REQ_P23 Register 0x2C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF ACMP_OPA_SRST_REQ ACMP_OPA_SRST_REQ 10 1 read-write ADC_SRST_REQ ADC_SRST_REQ 8 1 read-write TIM14_SRST_REQ TIM14_SRST_REQ 0 1 read-write TIM15_SRST_REQ TIM15_SRST_REQ 1 1 read-write TIM16_SRST_REQ TIM16_SRST_REQ 2 1 read-write TIM17_SRST_REQ TIM17_SRST_REQ 3 1 read-write TIM1_SRST_REQ TIM1_SRST_REQ 12 1 read-write TIM3_SRST_REQ TIM3_SRST_REQ 13 1 read-write STATUS0 STATUS0 Register 0x110 32 read-write n 0x10000B 0xFFFFFFFF CVM_EVENT CVM_EVENT 2 1 read-write DEBUG_VALID_EVENT DEBUG_VALID_EVENT 12 1 read-write IO_WAKEUP_EVENT IO_WAKEUP_EVENT 11 1 read-write IWDTRST_EVENT IWDTRST_EVENT 7 1 read-write LOCKUP_EVENT LOCKUP_EVENT 9 1 read-write LVD_EVENT LVD_EVENT 4 1 read-write LVR_EVENT LVR_EVENT 3 1 read-write NRST_EVENT NRST_EVENT 5 1 read-write OSCEN_CFGERR_EVENT OSCEN_CFGERR_EVENT 28 1 read-write OSC_MISS_EVENT OSC_MISS_EVENT 18 1 read-write PLLEN_CFGERR_EVENT PLLEN_CFGERR_EVENT 29 1 read-write PLLSRC_CFGERR_EVENT PLLSRC_CFGERR_EVENT 25 1 read-write PLL_MISS_MASK PLL_MISS_MASK 20 1 read-write POC_EVENT POC_EVENT 1 1 read-write POR_EVENT POR_EVENT 0 1 read-write RCHEN_CFGERR_EVENT RCHEN_CFGERR_EVENT 27 1 read-write RCH_MISS_EVENT RCH_MISS_MEVENT 16 1 read-write SCLKSEL_CFGERR_EVENT SCLKSEL_CFGERR_EVENT 24 1 read-write SRST_EVENT SRST_EVENT 8 1 read-write SYSCLKMUX_ERR_EVENT SYSCLKMUX_ERR_EVENT 22 1 read-write SYSCLKMUX_RST_EVENT SYSCLKMUX_RST_EVENT 10 1 read-write WDTRST_EVENT WDTRST_EVENT 6 1 read-write STATUS1 STATUS1 Register 0x120 32 read-only n 0x0 0xFFFFFFFF BGRFLAG BGRFLAG 11 1 read-only CVMFLAG CVMFLAG 9 1 read-only IWDT_INTR IWDT_INTR 13 1 read-only LVDFLAG LVDFLAG 7 1 read-only OSCSTOP OSCSTOP 0 1 read-only PLL_LOCK PLL_LOCK 5 1 read-only RCHSTB RCHSTB 3 1 read-only VERSION VERSION Register 0xC00 32 read-only n 0xD6930 0xFFFFFFFF WAKEUP_CTRL WAKEUP_CTRL Register 0x38 32 read-write n 0x0 0xFFFFFFFF DEBUG_WAKEUPEN DEBUG_WAKEUPEN 4 1 read-write IO_WAKEUPEN IO_WAKEUPEN 0 1 read-write IWDT_WAKEUPEN IWDT_WAKEUPEN 2 1 read-write LVD_WAKEUPEN LVD_WAKEUPEN 8 1 read-write WT_WAKEUPEN WT_WAKEUPEN 16 1 read-write WT_ALERM WT_ALERM Register 0x84 32 read-write n 0x0 0xFFFFFFFF ALERM ALERM 0 8 read-write WT_CNT WT_CNT Register 0x88 32 read-write n 0x0 0xFFFFFFFF WT_CNT WT_CNT 0 23 read-only WT_CTRL WT_CTRL Register 0x80 32 read-write n 0x0 0xFFFFFFFF BK_SEL BK_SEL 8 2 read-write BUZ_SEL BUZ_SEL 4 2 read-write INT INT 24 1 read-write INTEN INTEN 16 1 read-write WT_EN WT_EN 0 1 read-write CRC CRC CRC 0x40020000 0x0 0xB0 registers n CTRL CRC_CTRL 0x60 32 read-write n 0x0 0xFFFFFFFF CRC_BYTE crc_byte 8 2 read-write CRC_GPS crc_gps 24 2 read-write CRC_LM crc_lm 16 1 read-write RESET reset 0 1 write-only RESET_CRC reset_crc 1 1 write-only DATA CRC_DATA 0x64 32 read-write n 0x0 0xFFFFFFFF RESULT CRC_RESULT 0x68 32 read-write n 0x0 0xFFFFFFFF DMA DMA module DMA 0x40086000 0x0 0xD00 registers n DMA DMA Interrupt 11 ACTIVE Active Register 0xC8 32 read-only n 0x0 0xFFFFFFFF ALT_BASE_PTR Channel Standby Control Base Address Pointer Register 0x8 32 read-only n 0x10 0xFFFFFFFF BASE_PTR Channel Control Base Address Pointer Register 0x4 32 read-write n 0x0 0xFFFFFFFF BUS_ERR Bus Error Register 0xD4 32 read-write n 0x0 0xFFFFFFFF CFG DMA Configure Register 0x0 32 read-write n 0x0 0xFFFFFFFF CTRL_PORT DMA PORT CONTROL 5 3 read-write ENABLE DMA ENABLE 0 1 read-write RESET DMA RESET 31 1 read-write CFG_ERR Configure Error Register 0xD0 32 read-write n 0x0 0xFFFFFFFF CTRL0 DMA Channel n Control Register 0x20 32 read-write n 0x0 0xFFFFFFFF BUSERR_INTREN bus error interrupt enable of channel n 24 1 read-write CFGERR_INTREN configuration error interrupt enable of channel n 25 1 read-write DMADONE_INTREN DMA completes the interrupt enable of channel n 28 1 read-write ENABLE Channel n enable 0 1 read-write PRIORITY priority setting of Channel n 5 1 read-write PRI_ALT Select the pointer of the main / standby base of n channel 2 1 read-write REQ0_MASK Channel n request 0 shielding 15 1 read-write REQ0_SEL Channel n request option 0 8 5 read-write REQ1_MASK Channel n request 1 shielding 23 1 read-write REQ1_SEL Channel n request option 1 16 5 read-write USE_BURST Channel n uses continuous transmission 4 1 read-write CTRL1 DMA Channel n Control Register 0x24 32 read-write n 0x0 0xFFFFFFFF BUSERR_INTREN bus error interrupt enable of channel n 24 1 read-write CFGERR_INTREN configuration error interrupt enable of channel n 25 1 read-write DMADONE_INTREN DMA completes the interrupt enable of channel n 28 1 read-write ENABLE Channel n enable 0 1 read-write PRIORITY priority setting of Channel n 5 1 read-write PRI_ALT Select the pointer of the main / standby base of n channel 2 1 read-write REQ0_MASK Channel n request 0 shielding 15 1 read-write REQ0_SEL Channel n request option 0 8 5 read-write REQ1_MASK Channel n request 1 shielding 23 1 read-write REQ1_SEL Channel n request option 1 16 5 read-write USE_BURST Channel n uses continuous transmission 4 1 read-write CTRL2 DMA Channel n Control Register 0x28 32 read-write n 0x0 0xFFFFFFFF BUSERR_INTREN bus error interrupt enable of channel n 24 1 read-write CFGERR_INTREN configuration error interrupt enable of channel n 25 1 read-write DMADONE_INTREN DMA completes the interrupt enable of channel n 28 1 read-write ENABLE Channel n enable 0 1 read-write PRIORITY priority setting of Channel n 5 1 read-write PRI_ALT Select the pointer of the main / standby base of n channel 2 1 read-write REQ0_MASK Channel n request 0 shielding 15 1 read-write REQ0_SEL Channel n request option 0 8 5 read-write REQ1_MASK Channel n request 1 shielding 23 1 read-write REQ1_SEL Channel n request option 1 16 5 read-write USE_BURST Channel n uses continuous transmission 4 1 read-write CTRL3 DMA Channel n Control Register 0x2C 32 read-write n 0x0 0xFFFFFFFF BUSERR_INTREN bus error interrupt enable of channel n 24 1 read-write CFGERR_INTREN configuration error interrupt enable of channel n 25 1 read-write DMADONE_INTREN DMA completes the interrupt enable of channel n 28 1 read-write ENABLE Channel n enable 0 1 read-write PRIORITY priority setting of Channel n 5 1 read-write PRI_ALT Select the pointer of the main / standby base of n channel 2 1 read-write REQ0_MASK Channel n request 0 shielding 15 1 read-write REQ0_SEL Channel n request option 0 8 5 read-write REQ1_MASK Channel n request 1 shielding 23 1 read-write REQ1_SEL Channel n request option 1 16 5 read-write USE_BURST Channel n uses continuous transmission 4 1 read-write CTRL4 DMA Channel n Control Register 0x30 32 read-write n 0x0 0xFFFFFFFF BUSERR_INTREN bus error interrupt enable of channel n 24 1 read-write CFGERR_INTREN configuration error interrupt enable of channel n 25 1 read-write DMADONE_INTREN DMA completes the interrupt enable of channel n 28 1 read-write ENABLE Channel n enable 0 1 read-write PRIORITY priority setting of Channel n 5 1 read-write PRI_ALT Select the pointer of the main / standby base of n channel 2 1 read-write REQ0_MASK Channel n request 0 shielding 15 1 read-write REQ0_SEL Channel n request option 0 8 5 read-write REQ1_MASK Channel n request 1 shielding 23 1 read-write REQ1_SEL Channel n request option 1 16 5 read-write USE_BURST Channel n uses continuous transmission 4 1 read-write CTRL5 DMA Channel n Control Register 0x34 32 read-write n 0x0 0xFFFFFFFF BUSERR_INTREN bus error interrupt enable of channel n 24 1 read-write CFGERR_INTREN configuration error interrupt enable of channel n 25 1 read-write DMADONE_INTREN DMA completes the interrupt enable of channel n 28 1 read-write ENABLE Channel n enable 0 1 read-write PRIORITY priority setting of Channel n 5 1 read-write PRI_ALT Select the pointer of the main / standby base of n channel 2 1 read-write REQ0_MASK Channel n request 0 shielding 15 1 read-write REQ0_SEL Channel n request option 0 8 5 read-write REQ1_MASK Channel n request 1 shielding 23 1 read-write REQ1_SEL Channel n request option 1 16 5 read-write USE_BURST Channel n uses continuous transmission 4 1 read-write DONE Done Register 0xCC 32 read-write n 0x0 0xFFFFFFFF REQUEST_ON DMA Request Wait Status Register 0xC4 32 read-only n 0x0 0xFFFFFFFF STATUS DMA Status Control Register 0xC0 32 read-only n 0x0 0xFFFFFFFF CHNL_NUM_MINUS1 DMA chnnel minus 1 16 5 read-only CREQ_NUM_MINUS1 DMA request number minus 1 8 5 read-only ENABLE DMA Enable bit 0 1 read-only STATE DMA Status 4 4 read-only SW_REQ Software Request Register 0xC 32 write-only n 0x0 0xFFFFFFFF VERSION DMA Version Register 0xC00 32 read-only n 0xD6510 0xFFFFFFFF EFLASH EFLASH EFLASH 0x40088000 0x0 0x50 registers n SYS SYS Interrupt 13 ADDR Flash Address Register 0x10 32 read-write n 0x0 0xFFFFFFFF BTADDR BOOT Partition address information Register 0x3C 32 read-only n 0x0 0xFFFFFFFF EDADDR Protect Interrupt Clear 16 16 read-only STADDR Complete Operation Clear 0 16 read-only CCLR Flash Control Clear Register 0x4 32 write-only n 0x0 0xFFFFFFFF BOOTKEYEN BOOTKEYEN 8 1 write-only MASSEN MASSEN 3 1 write-only NVREN NVREN 5 1 write-only PAGEEN PAGEEN 2 1 write-only PROGEN PROGEN 1 1 write-only RDEN RDEN 4 1 write-only USR1KEYEN USR1KEYEN 9 1 write-only USR2KEYEN USR2KEYEN 10 1 write-only CFG Flash Configure Register 0xC 32 read-write n 0x0 0xFFFFFFFF NODATAPRF NODATAPRF 4 1 read-write PREFETCHEN PREFETCHEN 2 1 read-write READCFG READCFG 0 2 read-write CSET Flash Control Set Register 0x0 32 write-only n 0x0 0xFFFFFFFF BOOTKEYEN BOOTKEYEN 8 1 write-only MASSEN MASSEN 3 1 write-only NVREN NVREN 5 1 write-only OPSTART OPSTART 0 1 write-only PAGEEN PAGEEN 2 1 write-only PROGEN PROGEN 1 1 write-only RDEN RDEN 4 1 write-only USR1KEYEN USR1KEYEN 9 1 write-only USR2KEYEN USR2KEYEN 10 1 write-only CTRL Flash Control Status Register 0x8 32 read-only n 0x0 0xFFFFFFFF BOOTKEYS BOOTKEYS 8 1 write-only MASSS MASSS 3 1 write-only NVRS NVRS 5 1 write-only PAGES PAGES 2 1 write-only PROGS PROGS 1 1 write-only RDS RDS 4 1 write-only USR1KEYS USR1KEYS 9 1 write-only USR2KEYS USR2KEYS 10 1 write-only DATA Flash Data Register 0x14 32 read-write n 0x0 0xFFFFFFFF FEED Flash feed Register 0x18 32 write-only n 0x0 0xFFFFFFFF ICR Flash Interrupt Clear Register 0x24 32 write-only n 0x0 0xFFFFFFFF COMPCLR Complete Operation Clear 0 1 write-only DRDERRCLR READ DATA ERROR Interrupt Clear 4 1 write-only ERRORCLR Error Interrupt Clear 2 1 write-only PROTCLR Protect Interrupt Clear 1 1 write-only RCHOFFCLR RCH OFF Interrupt Clear 3 1 write-only IEN Flash Interrupt Enable Register 0x1C 32 read-write n 0x0 0xFFFFFFFF COMPINTEN Complete Operation Interrupt Enable 0 1 read-write DRDERRINTEN READ DATA ERROR Interrupt Enable 4 1 read-write ERRINTEN Error Interrupt Enable 2 1 read-write PROTINTEN Protect Interrupt Enable 1 1 read-write RCHOFFINTEN RCH OFF Interrupt Enable 3 1 read-write ISR Flash Interrupt Status Register 0x20 32 read-only n 0x0 0xFFFFFFFF COMPLETE Complete Operation Status 0 1 read-only DRDERR READ DATA ERROR Interrupt Status 4 1 read-only ERROR Error Interrupt Status 2 1 read-only PROTECT Protect Interrupt Status 1 1 read-only RCHOFF RCH OFF Interrupt Status 3 1 read-only KEY1 Flash Key1 Match Register 0x2C 32 write-only n 0x0 0xFFFFFFFF KEY2 Flash Key2 Match Register 0x30 32 write-only n 0x0 0xFFFFFFFF KEY3 Flash Key3 Match Register 0x34 32 write-only n 0x0 0xFFFFFFFF KEY4 Flash Key4 Match Register 0x38 32 write-only n 0x0 0xFFFFFFFF STATUS Flash Status Register 0x28 32 read-only n 0x0 0xFFFFFFFF BOOTCRCEN BOOT CRC ENABLE Status 8 1 read-only BOOTCRCOK BOOT partition CRC check Status 24 1 read-only BOOTKEYOK BOOT key matching Status 16 1 read-only BOOTPAREN BOOT partition Status 0 1 read-only USR1CRCEN USR1 CRC ENABLE Status 9 1 read-only USR1CRCOK USR1 partition CRC check Status 25 1 read-only USR1KEYOK USR1 key matching Status 17 1 read-only USR1PAREN USR1 partition Status 1 1 read-only USR2CRCEN USR1 CRC ENABLE Status 10 1 read-only USR2CRCOK USR2 partition CRC check Status 26 1 read-only USR2KEYOK USR2 key matching Status 18 1 read-only USR2PAREN USR1 partition Status 2 1 read-only U1ADDR User1 Partition address information Register 0x40 32 read-only n 0x0 0xFFFFFFFF EDADDR Protect Interrupt Clear 16 16 read-only STADDR Complete Operation Clear 0 16 read-only U2ADDR User2 Partition address information Register 0x44 32 read-only n 0x0 0xFFFFFFFF EDADDR Protect Interrupt Clear 16 16 read-only STADDR Complete Operation Clear 0 16 read-only ERU ERU ERU 0x40083000 0x0 0x30 registers n ERU0 ERU0 Interrupt 28 ERU1 ERU1 Interrupt 29 ERU2 ERU2 Interrupt 30 ERU3 ERU3 Interrupt 31 EXICON0 ERU Input Control Register 0 0x10 32 read-write n 0x0 0xFFFFFFFF APOL The polarity of the input A choice 18 1 read-write BPOL The polarity of the input B choice 19 1 read-write ERSOSEL ERS0 input source Selecet 16 2 read-write FE ETL0 Falling Edge Test Enable 3 1 read-write FL ETL0 status flag 8 1 read-write LD ETL0 Reconstruction of the Status Flag Level Detection 1 1 read-write OCS ETL0 Output Trigger Pulse Output Channel Choice 4 3 read-write PE ETL0 Output Trigger Pulse Enable 0 1 read-write RE ETL0 Rising Edge Test Enable 2 1 read-write EXICON1 ERU Input Control Register 0 0x14 32 read-write n 0x0 0xFFFFFFFF APOL The polarity of the input A choice 18 1 read-write BPOL The polarity of the input B choice 19 1 read-write ERSOSEL ERS0 input source Selecet 16 2 read-write FE ETL0 Falling Edge Test Enable 3 1 read-write FL ETL0 status flag 8 1 read-write LD ETL0 Reconstruction of the Status Flag Level Detection 1 1 read-write OCS ETL0 Output Trigger Pulse Output Channel Choice 4 3 read-write PE ETL0 Output Trigger Pulse Enable 0 1 read-write RE ETL0 Rising Edge Test Enable 2 1 read-write EXICON2 ERU Input Control Register 0 0x18 32 read-write n 0x0 0xFFFFFFFF APOL The polarity of the input A choice 18 1 read-write BPOL The polarity of the input B choice 19 1 read-write ERSOSEL ERS0 input source Selecet 16 2 read-write FE ETL0 Falling Edge Test Enable 3 1 read-write FL ETL0 status flag 8 1 read-write LD ETL0 Reconstruction of the Status Flag Level Detection 1 1 read-write OCS ETL0 Output Trigger Pulse Output Channel Choice 4 3 read-write PE ETL0 Output Trigger Pulse Enable 0 1 read-write RE ETL0 Rising Edge Test Enable 2 1 read-write EXICON3 ERU Input Control Register 0 0x1C 32 read-write n 0x0 0xFFFFFFFF APOL The polarity of the input A choice 18 1 read-write BPOL The polarity of the input B choice 19 1 read-write ERSOSEL ERS0 input source Selecet 16 2 read-write FE ETL0 Falling Edge Test Enable 3 1 read-write FL ETL0 status flag 8 1 read-write LD ETL0 Reconstruction of the Status Flag Level Detection 1 1 read-write OCS ETL0 Output Trigger Pulse Output Channel Choice 4 3 read-write PE ETL0 Output Trigger Pulse Enable 0 1 read-write RE ETL0 Rising Edge Test Enable 2 1 read-write EXISEL ERU Input Select Register 0x0 32 read-write n 0x0 0xFFFFFFFF IN0_SELA A0 Event Source Select 0 3 read-write IN0_SELB B0 Event Source Select 4 3 read-write IN1_SELA A1 Event Source Select 8 3 read-write IN1_SELB B1 Event Source Select 12 3 read-write IN2_SELA A2 Event Source Select 16 3 read-write IN2_SELB B2 Event Source Select 20 3 read-write IN3_SELA A3 Event Source Select 24 3 read-write IN3_SELB B3 Event Source Select 28 3 read-write EXOCON0 ERU Output Control Register 0 0x20 32 read-write n 0x0 0xFFFFFFFF GEEN Door control events enable 2 1 read-write GP Model test results of gating options 4 2 read-write IPEN0 ETL0 Model test enable 16 1 read-write IPEN1 ETL1 Model test enable 17 1 read-write IPEN2 ETL2 Model test enable 18 1 read-write IPEN3 ETL3 Model test enable 19 1 read-write ISS Internal trigger source choice 0 2 read-write PDR Model test results flag 3 1 read-only EXOCON1 ERU Output Control Register 0 0x24 32 read-write n 0x0 0xFFFFFFFF GEEN Door control events enable 2 1 read-write GP Model test results of gating options 4 2 read-write IPEN0 ETL0 Model test enable 16 1 read-write IPEN1 ETL1 Model test enable 17 1 read-write IPEN2 ETL2 Model test enable 18 1 read-write IPEN3 ETL3 Model test enable 19 1 read-write ISS Internal trigger source choice 0 2 read-write PDR Model test results flag 3 1 read-only EXOCON2 ERU Output Control Register 0 0x28 32 read-write n 0x0 0xFFFFFFFF GEEN Door control events enable 2 1 read-write GP Model test results of gating options 4 2 read-write IPEN0 ETL0 Model test enable 16 1 read-write IPEN1 ETL1 Model test enable 17 1 read-write IPEN2 ETL2 Model test enable 18 1 read-write IPEN3 ETL3 Model test enable 19 1 read-write ISS Internal trigger source choice 0 2 read-write PDR Model test results flag 3 1 read-only EXOCON3 ERU Output Control Register 0 0x2C 32 read-write n 0x0 0xFFFFFFFF GEEN Door control events enable 2 1 read-write GP Model test results of gating options 4 2 read-write IPEN0 ETL0 Model test enable 16 1 read-write IPEN1 ETL1 Model test enable 17 1 read-write IPEN2 ETL2 Model test enable 18 1 read-write IPEN3 ETL3 Model test enable 19 1 read-write ISS Internal trigger source choice 0 2 read-write PDR Model test results flag 3 1 read-only I2C I2C I2C 0x40097000 0x0 0x100 registers n I2C I2C Interrupt 4 ADDR I2C Address Register 0xC 32 read-write n 0x0 0xFFFFFFFF ADDR Address 1 7 read-write GC Broadcast Ack Signal 0 1 read-write CCLR I2C Control Clear Register 0x4 32 write-only n 0x0 0xFFFFFFFF AA ACK bit 2 1 write-only CR0 CR0 0 1 write-only CR1 CR1 1 1 write-only CR2 CR2 7 1 write-only CR3 CR3 9 1 write-only EN Enable 6 1 write-only SI Clear Interrupt bit 3 1 write-only STA Send Start Bit 5 1 write-only STO Send Stop Bit 4 1 write-only CSET I2C Control Set Register 0x0 32 write-only n 0x0 0xFFFFFFFF AA ACK bit 2 1 write-only CR0 CR0 0 1 write-only CR1 CR1 1 1 write-only CR2 CR2 7 1 write-only CR3 CR3 9 1 write-only EN Enable 6 1 write-only STA Send Start Bit 5 1 write-only STO Send Stop Bit 4 1 write-only CSR I2C Control Status Register 0x8 32 read-only n 0x0 0xFFFFFFFF AA ACK bit 2 1 read-only CR0 CR0 0 1 read-only CR1 CR1 1 1 read-only CR2 CR2 7 1 read-only CR3 CR3 9 1 read-only EN Enable 6 1 read-only SI Clear Interrupt bit 3 1 read-only STA Send Start Bit 5 1 read-only STO Send Stop Bit 4 1 read-only DATA I2C Data Register 0x10 32 read-write n 0x0 0xFFFFFFFF DATA I2C Data Register 0 8 read-write MEXT TMEX timeout detection Register 0x20 32 read-write n 0x0 0xFFFFFFFF MEXT TMEX timeout detection Register 0 16 read-write SCLH SCLH 0x1C 32 read-write n 0x0 0xFFFFFFFF SCLH SCLH 0 16 read-write SCLL SCLL 0x18 32 read-write n 0x0 0xFFFFFFFF SCLL SCLL 0 16 read-write SEXT SEXT timeout detection Register 0x24 32 read-write n 0x0 0xFFFFFFFF SEXT SEXT timeout detection Register 0 16 read-write SR I2C Status Register 0x14 32 read-only n 0x0 0xFFFFFFFF STAT I2C Status 3 5 read-only TMOUT TMOUT 2 1 read-only TOUT TOUT 0 1 read-only TSOUT TSOUT 1 1 read-only TOUT timeout detection Register 0x28 32 read-write n 0x0 0xFFFFFFFF TOUT timeout detection Register 0 16 read-write LED LED LED 0x400AE000 0x0 0x100 registers n LED LED Interrupt 21 COMSEL COMSEL Register 0x14 32 read-write n 0x0 0xFFFFFFFF CTRL LED_CTRL Register 0x0 32 read-write n 0x0 0xFFFFFFFF COMIF_IE COMIF_IE 3 1 read-write LEDIF_IE LEDIF_IE 4 1 read-write LEDMD LEDMD 6 1 read-write LEDON LEDON 7 1 read-write MODE MODE 5 1 read-write UPDMODE UPDMODE 1 1 read-write DISCOM DISCOM 0x8 32 read-write n 0x0 0xFFFFFFFF DISCOM DISCOM 0 8 read-write IF LED_IF Register 0x4 32 read-write n 0x0 0xFFFFFFFF COMIF COMIF 3 1 read-write IDLE_ST IDLE_ST 2 1 read-only LEDIF LEDIF 4 1 read-write LEDDZ LEDDZ 0xC 32 read-write n 0x0 0xFFFFFFFF LEDDZ LEDDZ 0 8 read-write RAM0 LED_RAM0 Register 0x20 32 read-write n 0x0 0xFFFFFFFF RAM1 LED_RAM1 0x24 32 read-write n 0x0 0xFFFFFFFF RAM2 LED_RAM2 Register 0x28 32 read-write n 0x0 0xFFFFFFFF RAM3 LED_RAM3 Register 0x2C 32 read-write n 0x0 0xFFFFFFFF SEGSEL SEGSEL Register 0x10 32 read-write n 0x0 0xFFFFFFFF PA PA P0RT 0x40000000 0x0 0x1000 registers n PA PA Interrupt 16 CFG0 PORT Control Register 0x0 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG1 PORT Control Register 0x4 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG10 PORT Control Register 0x28 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG11 PORT Control Register 0x2C 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG12 PORT Control Register 0x30 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG13 PORT Control Register 0x34 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG14 PORT Control Register 0x38 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG15 PORT Control Register 0x3C 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG2 PORT Control Register 0x8 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG3 PORT Control Register 0xC 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG4 PORT Control Register 0x10 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG5 PORT Control Register 0x14 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG6 PORT Control Register 0x18 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG7 PORT Control Register 0x1C 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG8 PORT Control Register 0x20 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG9 PORT Control Register 0x24 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write GCFG0 Global Configuration Register 0 0xD8 32 write-only n 0x0 0xFFFFFFFF GMASK0 GMASK0 0 1 write-only GMASK1 GMASK1 1 1 write-only GMASK10 GMASK10 10 1 write-only GMASK11 GMASK11 11 1 write-only GMASK12 GMASK12 12 1 write-only GMASK13 GMASK13 13 1 write-only GMASK14 GMASK14 14 1 write-only GMASK15 GMASK15 15 1 write-only GMASK16 GMASK16 16 1 write-only GMASK17 GMASK17 17 1 write-only GMASK18 GMASK18 18 1 write-only GMASK19 GMASK19 19 1 write-only GMASK2 GMASK2 2 1 write-only GMASK20 GMASK20 20 1 write-only GMASK21 GMASK21 21 1 write-only GMASK22 GMASK22 22 1 write-only GMASK23 GMASK23 23 1 write-only GMASK24 GMASK24 24 1 write-only GMASK25 GMASK25 25 1 write-only GMASK26 GMASK26 26 1 write-only GMASK27 GMASK27 27 1 write-only GMASK28 GMASK28 28 1 write-only GMASK29 GMASK29 29 1 write-only GMASK3 GMASK3 3 1 write-only GMASK30 GMASK30 30 1 write-only GMASK31 GMASK31 31 1 write-only GMASK4 GMASK4 4 1 write-only GMASK5 GMASK5 5 1 write-only GMASK6 GMASK6 6 1 write-only GMASK7 GMASK7 7 1 write-only GMASK8 GMASK8 8 1 write-only GMASK9 GMASK9 9 1 write-only GCFG1 0xDC -1 read-write n GCFGMASK GLOBAL CONFIGUE MASK REGISTER 0xD0 32 read-write n 0xFFFFFFFF 0x0 GMASK0 GMASK0 0 1 read-write GMASK1 GMASK1 1 1 read-write GMASK10 GMASK10 10 1 read-write GMASK11 GMASK11 11 1 read-write GMASK12 GMASK12 12 1 read-write GMASK13 GMASK13 13 1 read-write GMASK14 GMASK14 14 1 read-write GMASK15 GMASK15 15 1 read-write GMASK16 GMASK16 16 1 read-write GMASK17 GMASK17 17 1 read-write GMASK18 GMASK18 18 1 read-write GMASK19 GMASK19 19 1 read-write GMASK2 GMASK2 2 1 read-write GMASK20 GMASK20 20 1 read-write GMASK21 GMASK21 21 1 read-write GMASK22 GMASK22 22 1 read-write GMASK23 GMASK23 23 1 read-write GMASK24 GMASK24 24 1 read-write GMASK25 GMASK25 25 1 read-write GMASK26 GMASK26 26 1 read-write GMASK27 GMASK27 27 1 read-write GMASK28 GMASK28 28 1 read-write GMASK29 GMASK29 29 1 read-write GMASK3 GMASK3 3 1 read-write GMASK30 GMASK30 30 1 read-write GMASK31 GMASK31 31 1 read-write GMASK4 GMASK4 4 1 read-write GMASK5 GMASK5 5 1 read-write GMASK6 GMASK6 6 1 read-write GMASK7 GMASK7 7 1 read-write GMASK8 GMASK8 8 1 read-write GMASK9 GMASK9 9 1 read-write INTBV Interrupt Double Edge Register 0xB8 32 read-write n 0x0 0xFFFFFFFF GPIO0 GPIO0 Bipolar Interrupt Enable 0 1 read-write GPIO1 GPIO1 Bipolar Interrupt Enable 1 1 read-write GPIO10 GPIO10 Bipolar Interrupt Enable 10 1 read-write GPIO11 GPIO11 Bipolar Interrupt Enable 11 1 read-write GPIO12 GPIO12 Bipolar Interrupt Enable 12 1 read-write GPIO13 GPIO13 Bipolar Interrupt Enable 13 1 read-write GPIO14 GPIO14 Bipolar Interrupt Enable 14 1 read-write GPIO15 GPIO15 Bipolar Interrupt Enable 15 1 read-write GPIO2 GPIO2 Bipolar Interrupt Enable 2 1 read-write GPIO3 GPIO3 Bipolar Interrupt Enable 3 1 read-write GPIO4 GPIO4 Bipolar Interrupt Enable 4 1 read-write GPIO5 GPIO5 Bipolar Interrupt Enable 5 1 read-write GPIO6 GPIO6 Bipolar Interrupt Enable 6 1 read-write GPIO7 GPIO7 Bipolar Interrupt Enable 7 1 read-write GPIO8 GPIO8 Bipolar Interrupt Enable 8 1 read-write GPIO9 GPIO9 Bipolar Interrupt Enable 9 1 read-write INTMASK Interrupt Mask Register 0xB0 32 read-write n 0xFFFFFFFF 0xFFFFFFFF GPIO0 GPIO0 Interrupt Mask 0 1 read-write GPIO1 GPIO1 Interrupt Mask 1 1 read-write GPIO10 GPIO10 Interrupt Mask 10 1 read-write GPIO11 GPIO11 Interrupt Mask 11 1 read-write GPIO12 GPIO12 Interrupt Mask 12 1 read-write GPIO13 GPIO13 Interrupt Mask 13 1 read-write GPIO14 GPIO14 Interrupt Mask 14 1 read-write GPIO15 GPIO15 Interrupt Mask 15 1 read-write GPIO2 GPIO2 Interrupt Mask 2 1 read-write GPIO3 GPIO3 Interrupt Mask 3 1 read-write GPIO4 GPIO4 Interrupt Mask 4 1 read-write GPIO5 GPIO5 Interrupt Mask 5 1 read-write GPIO6 GPIO6 Interrupt Mask 6 1 read-write GPIO7 GPIO7 Interrupt Mask 7 1 read-write GPIO8 GPIO8 Interrupt Mask 8 1 read-write GPIO9 GPIO9 Interrupt Mask 9 1 read-write INTPOL Interrupt Polarity Register 0xBC 32 read-write n 0x0 0xFFFFFFFF GPIO0 GPIO0 Interrupt Polarity Enable 0 1 read-write GPIO1 GPIO1 Interrupt Polarity Enable 1 1 read-write GPIO10 GPIO10 Interrupt Polarity Enable 10 1 read-write GPIO11 GPIO11 Interrupt Polarity Enable 11 1 read-write GPIO12 GPIO12 Interrupt Polarity Enable 12 1 read-write GPIO13 GPIO13 Interrupt Polarity Enable 13 1 read-write GPIO14 GPIO14 Interrupt Polarity Enable 14 1 read-write GPIO15 GPIO15 Interrupt Polarity Enable 15 1 read-write GPIO2 GPIO2 Interrupt Polarity Enable 2 1 read-write GPIO3 GPIO3 Interrupt Polarity Enable 3 1 read-write GPIO4 GPIO4 Interrupt Polarity Enable 4 1 read-write GPIO5 GPIO5 Interrupt Polarity Enable 5 1 read-write GPIO6 GPIO6 Interrupt Polarity Enable 6 1 read-write GPIO7 GPIO7 Interrupt Polarity Enable 7 1 read-write GPIO8 GPIO8 Interrupt Polarity Enable 8 1 read-write GPIO9 GPIO9 Interrupt Polarity Enable 9 1 read-write INTTYPE Interrupt Type Register 0xB4 32 read-write n 0x0 0xFFFFFFFF GPIO0 GPIO0 Interrupt Type Select 0 1 read-write GPIO1 GPIO1 Interrupt Type Select 1 1 read-write GPIO10 GPIO10 Interrupt Type Select 10 1 read-write GPIO11 GPIO11 Interrupt Type Select 11 1 read-write GPIO12 GPIO12 Interrupt Type Select 12 1 read-write GPIO13 GPIO13 Interrupt Type Select 13 1 read-write GPIO14 GPIO14 Interrupt Type Select 14 1 read-write GPIO15 GPIO15 Interrupt Type Select 15 1 read-write GPIO2 GPIO2 Interrupt Type Select 2 1 read-write GPIO3 GPIO3 Interrupt Type Select 3 1 read-write GPIO4 GPIO4 Interrupt Type Select 4 1 read-write GPIO5 GPIO5 Interrupt Type Select 5 1 read-write GPIO6 GPIO6 Interrupt Type Select 6 1 read-write GPIO7 GPIO7 Interrupt Type Select 7 1 read-write GPIO8 GPIO8 Interrupt Type Select 8 1 read-write GPIO9 GPIO9 Interrupt Type Select 9 1 read-write LOCK0 Configure LOCK Register 0 0xE0 32 read-write n 0x0 0xFFFFFFFF LOCKL0 LOCKL0 0 1 read-write LOCKL1 LOCKL1 1 1 read-write LOCKL10 LOCKL10 10 1 read-write LOCKL11 LOCKL11 11 1 read-write LOCKL12 LOCKL12 12 1 read-write LOCKL13 LOCKL13 13 1 read-write LOCKL14 LOCKL14 14 1 read-write LOCKL15 LOCKL15 15 1 read-write LOCKL2 LOCKL2 2 1 read-write LOCKL3 LOCKL3 3 1 read-write LOCKL4 LOCKL4 4 1 read-write LOCKL5 LOCKL5 5 1 read-write LOCKL6 LOCKL6 6 1 read-write LOCKL7 LOCKL7 7 1 read-write LOCKL8 LOCKL8 8 1 read-write LOCKL9 LOCKL9 9 1 read-write LOCKL_KEY LOCKL_KEY 16 16 read-write LOCK1 0xE4 -1 read-write n MIS Mask Interrupt Status Register 0xC4 32 read-write n 0x0 0xFFFFFFFF GPIO0 GPIO0 Masked Interrupt Status 0 1 read-write GPIO1 GPIO1 Masked Interrupt Status 1 1 read-write GPIO10 GPIO10 Masked Interrupt Status 10 1 read-write GPIO11 GPIO11 Masked Interrupt Status 11 1 read-write GPIO12 GPIO12 Masked Interrupt Status 12 1 read-write GPIO13 GPIO13 Masked Interrupt Status 13 1 read-write GPIO14 GPIO14 Masked Interrupt Status 14 1 read-write GPIO15 GPIO15 Masked Interrupt Status 15 1 read-write GPIO2 GPIO2 Masked Interrupt Status 2 1 read-write GPIO3 GPIO3 Masked Interrupt Status 3 1 read-write GPIO4 GPIO4 Masked Interrupt Status 4 1 read-write GPIO5 GPIO5 Masked Interrupt Status 5 1 read-write GPIO6 GPIO6 Masked Interrupt Status 6 1 read-write GPIO7 GPIO7 Masked Interrupt Status 7 1 read-write GPIO8 GPIO8 Masked Interrupt Status 8 1 read-write GPIO9 GPIO9 Masked Interrupt Status 9 1 read-write OUT Pin Output Register 0x90 32 read-write n 0x0 0xFFFFFFFF GPIO0 GPIO0 Output Status 0 1 read-write GPIO1 GPIO1 Output Status 1 1 read-write GPIO10 GPIO10 Output Status 10 1 read-write GPIO11 GPIO11 Output Status 11 1 read-write GPIO12 GPIO12 Output Status 12 1 read-write GPIO13 GPIO13 Output Status 13 1 read-write GPIO14 GPIO14 Output Status 14 1 read-write GPIO15 GPIO15 Output Status 15 1 read-write GPIO2 GPIO2 Output Status 2 1 read-write GPIO3 GPIO3 Output Status 3 1 read-write GPIO4 GPIO4 Output Status 4 1 read-write GPIO5 GPIO5 Output Status 5 1 read-write GPIO6 GPIO6 Output Status 6 1 read-write GPIO7 GPIO7 Output Status 7 1 read-write GPIO8 GPIO8 Output Status 8 1 read-write GPIO9 GPIO9 Output Status 9 1 read-write OUTCLR Pin Output Clear Register 0x98 32 read-write n 0x0 0xFFFFFFFF GPIO0 GPIO0 Output Clear 0 1 read-write GPIO1 GPIO1 Output Clear 1 1 read-write GPIO10 GPIO10 Output Clear 10 1 read-write GPIO11 GPIO11 Output Clear 11 1 read-write GPIO12 GPIO12 Output Clear 12 1 read-write GPIO13 GPIO13 Output Clear 13 1 read-write GPIO14 GPIO14 Output Clear 14 1 read-write GPIO15 GPIO15 Output Clear 15 1 read-write GPIO2 GPIO2 Output Clear 2 1 read-write GPIO3 GPIO3 Output Clear 3 1 read-write GPIO4 GPIO4 Output Clear 4 1 read-write GPIO5 GPIO5 Output Clear 5 1 read-write GPIO6 GPIO6 Output Clear 6 1 read-write GPIO7 GPIO7 Output Clear 7 1 read-write GPIO8 GPIO8 Output Clear 8 1 read-write GPIO9 GPIO9 Output Clear 9 1 read-write OUTEN Pin Output Enable Register 0xA0 32 read-write n 0x0 0xFFFFFFFF GPIO0 GPIO0 Output Enable 0 1 read-write GPIO1 GPIO1 Output Enable 1 1 read-write GPIO10 GPIO10 Output Enable 10 1 read-write GPIO11 GPIO11 Output Enable 11 1 read-write GPIO12 GPIO12 Output Enable 12 1 read-write GPIO13 GPIO13 Output Enable 13 1 read-write GPIO14 GPIO14 Output Enable 14 1 read-write GPIO15 GPIO15 Output Enable 15 1 read-write GPIO2 GPIO2 Output Enable 2 1 read-write GPIO3 GPIO3 Output Enable 3 1 read-write GPIO4 GPIO4 Output Enable 4 1 read-write GPIO5 GPIO5 Output Enable 5 1 read-write GPIO6 GPIO6 Output Enable 6 1 read-write GPIO7 GPIO7 Output Enable 7 1 read-write GPIO8 GPIO8 Output Enable 8 1 read-write GPIO9 GPIO9 Output Enable 9 1 read-write OUTSET Pin Output Set Register 0x94 32 read-write n 0x0 0xFFFFFFFF GPIO0 GPIO0 Output Set 0 1 read-write GPIO1 GPIO1 Output Set 1 1 read-write GPIO10 GPIO10 Output Set 10 1 read-write GPIO11 GPIO11 Output Set 11 1 read-write GPIO12 GPIO12 Output Set 12 1 read-write GPIO13 GPIO13 Output Set 13 1 read-write GPIO14 GPIO14 Output Set 14 1 read-write GPIO15 GPIO15 Output Set 15 1 read-write GPIO2 GPIO2 Output Set 2 1 read-write GPIO3 GPIO3 Output Set 3 1 read-write GPIO4 GPIO4 Output Set 4 1 read-write GPIO5 GPIO5 Output Set 5 1 read-write GPIO6 GPIO6 Output Set 6 1 read-write GPIO7 GPIO7 Output Set 7 1 read-write GPIO8 GPIO8 Output Set 8 1 read-write GPIO9 GPIO9 Output Set 9 1 read-write OUTTGL Pin Output Turn Register 0x9C 32 read-write n 0x0 0xFFFFFFFF GPIO0 GPIO0 Output Toggle 0 1 read-write GPIO1 GPIO1 Output Toggle 1 1 read-write GPIO10 GPIO10 Output Toggle 10 1 read-write GPIO11 GPIO11 Output Toggle 11 1 read-write GPIO12 GPIO12 Output Toggle 12 1 read-write GPIO13 GPIO13 Output Toggle 13 1 read-write GPIO14 GPIO14 Output Toggle 14 1 read-write GPIO15 GPIO15 Output Toggle 15 1 read-write GPIO2 GPIO2 Output Toggle 2 1 read-write GPIO3 GPIO3 Output Toggle 3 1 read-write GPIO4 GPIO4 Output Toggle 4 1 read-write GPIO5 GPIO5 Output Toggle 5 1 read-write GPIO6 GPIO6 Output Toggle 6 1 read-write GPIO7 GPIO7 Output Toggle 7 1 read-write GPIO8 GPIO8 Output Toggle 8 1 read-write GPIO9 GPIO9 Output Toggle 9 1 read-write PIN Pin Value Register 0x80 32 read-only n 0x0 0xFFFFFFFF GPIO0 GPIO0 Status 0 1 read-only GPIO1 GPIO1 Status 1 1 read-only GPIO10 GPIO10 Status 10 1 read-only GPIO11 GPIO11 Status 11 1 read-only GPIO12 GPIO12 Status 12 1 read-only GPIO13 GPIO13 Status 13 1 read-only GPIO14 GPIO14 Status 14 1 read-only GPIO15 GPIO15 Status 15 1 read-only GPIO2 GPIO2 Status 2 1 read-only GPIO3 GPIO3 Status 3 1 read-only GPIO4 GPIO4 Status 4 1 read-only GPIO5 GPIO5 Status 5 1 read-only GPIO6 GPIO6 Status 6 1 read-only GPIO7 GPIO7 Status 7 1 read-only GPIO8 GPIO8 Status 8 1 read-only GPIO9 GPIO9 Status 9 1 read-only RIS Original Interrupt Status Register 0xC0 32 read-write n 0x0 0xFFFFFFFF GPIO0 GPIO0 Original Interrupt Status 0 1 read-write GPIO1 GPIO1 Original Interrupt Status 1 1 read-write GPIO10 GPIO10 Original Interrupt Status 10 1 read-write GPIO11 GPIO11 Original Interrupt Status 11 1 read-write GPIO12 GPIO12 Original Interrupt Status 12 1 read-write GPIO13 GPIO13 Original Interrupt Status 13 1 read-write GPIO14 GPIO14 Original Interrupt Status 14 1 read-write GPIO15 GPIO15 Original Interrupt Status 15 1 read-write GPIO2 GPIO2 Original Interrupt Status 2 1 read-write GPIO3 GPIO3 Original Interrupt Status 3 1 read-write GPIO4 GPIO4 Original Interrupt Status 4 1 read-write GPIO5 GPIO5 Original Interrupt Status 5 1 read-write GPIO6 GPIO6 Original Interrupt Status 6 1 read-write GPIO7 GPIO7 Original Interrupt Status 7 1 read-write GPIO8 GPIO8 Original Interrupt Status 8 1 read-write GPIO9 GPIO9 Original Interrupt Status 9 1 read-write VERSION GPIO VERSION 0xC00 32 read-only n 0xD6610 0xFFFFFFFF PB PA P0RT 0x40001000 0x0 0x1000 registers n PB PB Interrupt 17 CFG0 PORT Control Register 0x0 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG1 PORT Control Register 0x4 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG10 PORT Control Register 0x28 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG11 PORT Control Register 0x2C 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG12 PORT Control Register 0x30 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG13 PORT Control Register 0x34 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG14 PORT Control Register 0x38 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG15 PORT Control Register 0x3C 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG2 PORT Control Register 0x8 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG3 PORT Control Register 0xC 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG4 PORT Control Register 0x10 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG5 PORT Control Register 0x14 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG6 PORT Control Register 0x18 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG7 PORT Control Register 0x1C 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG8 PORT Control Register 0x20 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG9 PORT Control Register 0x24 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write GCFG0 Global Configuration Register 0 0xD8 32 write-only n 0x0 0xFFFFFFFF GMASK0 GMASK0 0 1 write-only GMASK1 GMASK1 1 1 write-only GMASK10 GMASK10 10 1 write-only GMASK11 GMASK11 11 1 write-only GMASK12 GMASK12 12 1 write-only GMASK13 GMASK13 13 1 write-only GMASK14 GMASK14 14 1 write-only GMASK15 GMASK15 15 1 write-only GMASK16 GMASK16 16 1 write-only GMASK17 GMASK17 17 1 write-only GMASK18 GMASK18 18 1 write-only GMASK19 GMASK19 19 1 write-only GMASK2 GMASK2 2 1 write-only GMASK20 GMASK20 20 1 write-only GMASK21 GMASK21 21 1 write-only GMASK22 GMASK22 22 1 write-only GMASK23 GMASK23 23 1 write-only GMASK24 GMASK24 24 1 write-only GMASK25 GMASK25 25 1 write-only GMASK26 GMASK26 26 1 write-only GMASK27 GMASK27 27 1 write-only GMASK28 GMASK28 28 1 write-only GMASK29 GMASK29 29 1 write-only GMASK3 GMASK3 3 1 write-only GMASK30 GMASK30 30 1 write-only GMASK31 GMASK31 31 1 write-only GMASK4 GMASK4 4 1 write-only GMASK5 GMASK5 5 1 write-only GMASK6 GMASK6 6 1 write-only GMASK7 GMASK7 7 1 write-only GMASK8 GMASK8 8 1 write-only GMASK9 GMASK9 9 1 write-only GCFG1 0xDC -1 read-write n GCFGMASK GLOBAL CONFIGUE MASK REGISTER 0xD0 32 read-write n 0xFFFFFFFF 0x0 GMASK0 GMASK0 0 1 read-write GMASK1 GMASK1 1 1 read-write GMASK10 GMASK10 10 1 read-write GMASK11 GMASK11 11 1 read-write GMASK12 GMASK12 12 1 read-write GMASK13 GMASK13 13 1 read-write GMASK14 GMASK14 14 1 read-write GMASK15 GMASK15 15 1 read-write GMASK16 GMASK16 16 1 read-write GMASK17 GMASK17 17 1 read-write GMASK18 GMASK18 18 1 read-write GMASK19 GMASK19 19 1 read-write GMASK2 GMASK2 2 1 read-write GMASK20 GMASK20 20 1 read-write GMASK21 GMASK21 21 1 read-write GMASK22 GMASK22 22 1 read-write GMASK23 GMASK23 23 1 read-write GMASK24 GMASK24 24 1 read-write GMASK25 GMASK25 25 1 read-write GMASK26 GMASK26 26 1 read-write GMASK27 GMASK27 27 1 read-write GMASK28 GMASK28 28 1 read-write GMASK29 GMASK29 29 1 read-write GMASK3 GMASK3 3 1 read-write GMASK30 GMASK30 30 1 read-write GMASK31 GMASK31 31 1 read-write GMASK4 GMASK4 4 1 read-write GMASK5 GMASK5 5 1 read-write GMASK6 GMASK6 6 1 read-write GMASK7 GMASK7 7 1 read-write GMASK8 GMASK8 8 1 read-write GMASK9 GMASK9 9 1 read-write INTBV Interrupt Double Edge Register 0xB8 32 read-write n 0x0 0xFFFFFFFF GPIO0 GPIO0 Bipolar Interrupt Enable 0 1 read-write GPIO1 GPIO1 Bipolar Interrupt Enable 1 1 read-write GPIO10 GPIO10 Bipolar Interrupt Enable 10 1 read-write GPIO11 GPIO11 Bipolar Interrupt Enable 11 1 read-write GPIO12 GPIO12 Bipolar Interrupt Enable 12 1 read-write GPIO13 GPIO13 Bipolar Interrupt Enable 13 1 read-write GPIO14 GPIO14 Bipolar Interrupt Enable 14 1 read-write GPIO15 GPIO15 Bipolar Interrupt Enable 15 1 read-write GPIO2 GPIO2 Bipolar Interrupt Enable 2 1 read-write GPIO3 GPIO3 Bipolar Interrupt Enable 3 1 read-write GPIO4 GPIO4 Bipolar Interrupt Enable 4 1 read-write GPIO5 GPIO5 Bipolar Interrupt Enable 5 1 read-write GPIO6 GPIO6 Bipolar Interrupt Enable 6 1 read-write GPIO7 GPIO7 Bipolar Interrupt Enable 7 1 read-write GPIO8 GPIO8 Bipolar Interrupt Enable 8 1 read-write GPIO9 GPIO9 Bipolar Interrupt Enable 9 1 read-write INTMASK Interrupt Mask Register 0xB0 32 read-write n 0xFFFFFFFF 0xFFFFFFFF GPIO0 GPIO0 Interrupt Mask 0 1 read-write GPIO1 GPIO1 Interrupt Mask 1 1 read-write GPIO10 GPIO10 Interrupt Mask 10 1 read-write GPIO11 GPIO11 Interrupt Mask 11 1 read-write GPIO12 GPIO12 Interrupt Mask 12 1 read-write GPIO13 GPIO13 Interrupt Mask 13 1 read-write GPIO14 GPIO14 Interrupt Mask 14 1 read-write GPIO15 GPIO15 Interrupt Mask 15 1 read-write GPIO2 GPIO2 Interrupt Mask 2 1 read-write GPIO3 GPIO3 Interrupt Mask 3 1 read-write GPIO4 GPIO4 Interrupt Mask 4 1 read-write GPIO5 GPIO5 Interrupt Mask 5 1 read-write GPIO6 GPIO6 Interrupt Mask 6 1 read-write GPIO7 GPIO7 Interrupt Mask 7 1 read-write GPIO8 GPIO8 Interrupt Mask 8 1 read-write GPIO9 GPIO9 Interrupt Mask 9 1 read-write INTPOL Interrupt Polarity Register 0xBC 32 read-write n 0x0 0xFFFFFFFF GPIO0 GPIO0 Interrupt Polarity Enable 0 1 read-write GPIO1 GPIO1 Interrupt Polarity Enable 1 1 read-write GPIO10 GPIO10 Interrupt Polarity Enable 10 1 read-write GPIO11 GPIO11 Interrupt Polarity Enable 11 1 read-write GPIO12 GPIO12 Interrupt Polarity Enable 12 1 read-write GPIO13 GPIO13 Interrupt Polarity Enable 13 1 read-write GPIO14 GPIO14 Interrupt Polarity Enable 14 1 read-write GPIO15 GPIO15 Interrupt Polarity Enable 15 1 read-write GPIO2 GPIO2 Interrupt Polarity Enable 2 1 read-write GPIO3 GPIO3 Interrupt Polarity Enable 3 1 read-write GPIO4 GPIO4 Interrupt Polarity Enable 4 1 read-write GPIO5 GPIO5 Interrupt Polarity Enable 5 1 read-write GPIO6 GPIO6 Interrupt Polarity Enable 6 1 read-write GPIO7 GPIO7 Interrupt Polarity Enable 7 1 read-write GPIO8 GPIO8 Interrupt Polarity Enable 8 1 read-write GPIO9 GPIO9 Interrupt Polarity Enable 9 1 read-write INTTYPE Interrupt Type Register 0xB4 32 read-write n 0x0 0xFFFFFFFF GPIO0 GPIO0 Interrupt Type Select 0 1 read-write GPIO1 GPIO1 Interrupt Type Select 1 1 read-write GPIO10 GPIO10 Interrupt Type Select 10 1 read-write GPIO11 GPIO11 Interrupt Type Select 11 1 read-write GPIO12 GPIO12 Interrupt Type Select 12 1 read-write GPIO13 GPIO13 Interrupt Type Select 13 1 read-write GPIO14 GPIO14 Interrupt Type Select 14 1 read-write GPIO15 GPIO15 Interrupt Type Select 15 1 read-write GPIO2 GPIO2 Interrupt Type Select 2 1 read-write GPIO3 GPIO3 Interrupt Type Select 3 1 read-write GPIO4 GPIO4 Interrupt Type Select 4 1 read-write GPIO5 GPIO5 Interrupt Type Select 5 1 read-write GPIO6 GPIO6 Interrupt Type Select 6 1 read-write GPIO7 GPIO7 Interrupt Type Select 7 1 read-write GPIO8 GPIO8 Interrupt Type Select 8 1 read-write GPIO9 GPIO9 Interrupt Type Select 9 1 read-write LOCK0 Configure LOCK Register 0 0xE0 32 read-write n 0x0 0xFFFFFFFF LOCKL0 LOCKL0 0 1 read-write LOCKL1 LOCKL1 1 1 read-write LOCKL10 LOCKL10 10 1 read-write LOCKL11 LOCKL11 11 1 read-write LOCKL12 LOCKL12 12 1 read-write LOCKL13 LOCKL13 13 1 read-write LOCKL14 LOCKL14 14 1 read-write LOCKL15 LOCKL15 15 1 read-write LOCKL2 LOCKL2 2 1 read-write LOCKL3 LOCKL3 3 1 read-write LOCKL4 LOCKL4 4 1 read-write LOCKL5 LOCKL5 5 1 read-write LOCKL6 LOCKL6 6 1 read-write LOCKL7 LOCKL7 7 1 read-write LOCKL8 LOCKL8 8 1 read-write LOCKL9 LOCKL9 9 1 read-write LOCKL_KEY LOCKL_KEY 16 16 read-write LOCK1 0xE4 -1 read-write n MIS Mask Interrupt Status Register 0xC4 32 read-write n 0x0 0xFFFFFFFF GPIO0 GPIO0 Masked Interrupt Status 0 1 read-write GPIO1 GPIO1 Masked Interrupt Status 1 1 read-write GPIO10 GPIO10 Masked Interrupt Status 10 1 read-write GPIO11 GPIO11 Masked Interrupt Status 11 1 read-write GPIO12 GPIO12 Masked Interrupt Status 12 1 read-write GPIO13 GPIO13 Masked Interrupt Status 13 1 read-write GPIO14 GPIO14 Masked Interrupt Status 14 1 read-write GPIO15 GPIO15 Masked Interrupt Status 15 1 read-write GPIO2 GPIO2 Masked Interrupt Status 2 1 read-write GPIO3 GPIO3 Masked Interrupt Status 3 1 read-write GPIO4 GPIO4 Masked Interrupt Status 4 1 read-write GPIO5 GPIO5 Masked Interrupt Status 5 1 read-write GPIO6 GPIO6 Masked Interrupt Status 6 1 read-write GPIO7 GPIO7 Masked Interrupt Status 7 1 read-write GPIO8 GPIO8 Masked Interrupt Status 8 1 read-write GPIO9 GPIO9 Masked Interrupt Status 9 1 read-write OUT Pin Output Register 0x90 32 read-write n 0x0 0xFFFFFFFF GPIO0 GPIO0 Output Status 0 1 read-write GPIO1 GPIO1 Output Status 1 1 read-write GPIO10 GPIO10 Output Status 10 1 read-write GPIO11 GPIO11 Output Status 11 1 read-write GPIO12 GPIO12 Output Status 12 1 read-write GPIO13 GPIO13 Output Status 13 1 read-write GPIO14 GPIO14 Output Status 14 1 read-write GPIO15 GPIO15 Output Status 15 1 read-write GPIO2 GPIO2 Output Status 2 1 read-write GPIO3 GPIO3 Output Status 3 1 read-write GPIO4 GPIO4 Output Status 4 1 read-write GPIO5 GPIO5 Output Status 5 1 read-write GPIO6 GPIO6 Output Status 6 1 read-write GPIO7 GPIO7 Output Status 7 1 read-write GPIO8 GPIO8 Output Status 8 1 read-write GPIO9 GPIO9 Output Status 9 1 read-write OUTCLR Pin Output Clear Register 0x98 32 read-write n 0x0 0xFFFFFFFF GPIO0 GPIO0 Output Clear 0 1 read-write GPIO1 GPIO1 Output Clear 1 1 read-write GPIO10 GPIO10 Output Clear 10 1 read-write GPIO11 GPIO11 Output Clear 11 1 read-write GPIO12 GPIO12 Output Clear 12 1 read-write GPIO13 GPIO13 Output Clear 13 1 read-write GPIO14 GPIO14 Output Clear 14 1 read-write GPIO15 GPIO15 Output Clear 15 1 read-write GPIO2 GPIO2 Output Clear 2 1 read-write GPIO3 GPIO3 Output Clear 3 1 read-write GPIO4 GPIO4 Output Clear 4 1 read-write GPIO5 GPIO5 Output Clear 5 1 read-write GPIO6 GPIO6 Output Clear 6 1 read-write GPIO7 GPIO7 Output Clear 7 1 read-write GPIO8 GPIO8 Output Clear 8 1 read-write GPIO9 GPIO9 Output Clear 9 1 read-write OUTEN Pin Output Enable Register 0xA0 32 read-write n 0x0 0xFFFFFFFF GPIO0 GPIO0 Output Enable 0 1 read-write GPIO1 GPIO1 Output Enable 1 1 read-write GPIO10 GPIO10 Output Enable 10 1 read-write GPIO11 GPIO11 Output Enable 11 1 read-write GPIO12 GPIO12 Output Enable 12 1 read-write GPIO13 GPIO13 Output Enable 13 1 read-write GPIO14 GPIO14 Output Enable 14 1 read-write GPIO15 GPIO15 Output Enable 15 1 read-write GPIO2 GPIO2 Output Enable 2 1 read-write GPIO3 GPIO3 Output Enable 3 1 read-write GPIO4 GPIO4 Output Enable 4 1 read-write GPIO5 GPIO5 Output Enable 5 1 read-write GPIO6 GPIO6 Output Enable 6 1 read-write GPIO7 GPIO7 Output Enable 7 1 read-write GPIO8 GPIO8 Output Enable 8 1 read-write GPIO9 GPIO9 Output Enable 9 1 read-write OUTSET Pin Output Set Register 0x94 32 read-write n 0x0 0xFFFFFFFF GPIO0 GPIO0 Output Set 0 1 read-write GPIO1 GPIO1 Output Set 1 1 read-write GPIO10 GPIO10 Output Set 10 1 read-write GPIO11 GPIO11 Output Set 11 1 read-write GPIO12 GPIO12 Output Set 12 1 read-write GPIO13 GPIO13 Output Set 13 1 read-write GPIO14 GPIO14 Output Set 14 1 read-write GPIO15 GPIO15 Output Set 15 1 read-write GPIO2 GPIO2 Output Set 2 1 read-write GPIO3 GPIO3 Output Set 3 1 read-write GPIO4 GPIO4 Output Set 4 1 read-write GPIO5 GPIO5 Output Set 5 1 read-write GPIO6 GPIO6 Output Set 6 1 read-write GPIO7 GPIO7 Output Set 7 1 read-write GPIO8 GPIO8 Output Set 8 1 read-write GPIO9 GPIO9 Output Set 9 1 read-write OUTTGL Pin Output Turn Register 0x9C 32 read-write n 0x0 0xFFFFFFFF GPIO0 GPIO0 Output Toggle 0 1 read-write GPIO1 GPIO1 Output Toggle 1 1 read-write GPIO10 GPIO10 Output Toggle 10 1 read-write GPIO11 GPIO11 Output Toggle 11 1 read-write GPIO12 GPIO12 Output Toggle 12 1 read-write GPIO13 GPIO13 Output Toggle 13 1 read-write GPIO14 GPIO14 Output Toggle 14 1 read-write GPIO15 GPIO15 Output Toggle 15 1 read-write GPIO2 GPIO2 Output Toggle 2 1 read-write GPIO3 GPIO3 Output Toggle 3 1 read-write GPIO4 GPIO4 Output Toggle 4 1 read-write GPIO5 GPIO5 Output Toggle 5 1 read-write GPIO6 GPIO6 Output Toggle 6 1 read-write GPIO7 GPIO7 Output Toggle 7 1 read-write GPIO8 GPIO8 Output Toggle 8 1 read-write GPIO9 GPIO9 Output Toggle 9 1 read-write PIN Pin Value Register 0x80 32 read-only n 0x0 0xFFFFFFFF GPIO0 GPIO0 Status 0 1 read-only GPIO1 GPIO1 Status 1 1 read-only GPIO10 GPIO10 Status 10 1 read-only GPIO11 GPIO11 Status 11 1 read-only GPIO12 GPIO12 Status 12 1 read-only GPIO13 GPIO13 Status 13 1 read-only GPIO14 GPIO14 Status 14 1 read-only GPIO15 GPIO15 Status 15 1 read-only GPIO2 GPIO2 Status 2 1 read-only GPIO3 GPIO3 Status 3 1 read-only GPIO4 GPIO4 Status 4 1 read-only GPIO5 GPIO5 Status 5 1 read-only GPIO6 GPIO6 Status 6 1 read-only GPIO7 GPIO7 Status 7 1 read-only GPIO8 GPIO8 Status 8 1 read-only GPIO9 GPIO9 Status 9 1 read-only RIS Original Interrupt Status Register 0xC0 32 read-write n 0x0 0xFFFFFFFF GPIO0 GPIO0 Original Interrupt Status 0 1 read-write GPIO1 GPIO1 Original Interrupt Status 1 1 read-write GPIO10 GPIO10 Original Interrupt Status 10 1 read-write GPIO11 GPIO11 Original Interrupt Status 11 1 read-write GPIO12 GPIO12 Original Interrupt Status 12 1 read-write GPIO13 GPIO13 Original Interrupt Status 13 1 read-write GPIO14 GPIO14 Original Interrupt Status 14 1 read-write GPIO15 GPIO15 Original Interrupt Status 15 1 read-write GPIO2 GPIO2 Original Interrupt Status 2 1 read-write GPIO3 GPIO3 Original Interrupt Status 3 1 read-write GPIO4 GPIO4 Original Interrupt Status 4 1 read-write GPIO5 GPIO5 Original Interrupt Status 5 1 read-write GPIO6 GPIO6 Original Interrupt Status 6 1 read-write GPIO7 GPIO7 Original Interrupt Status 7 1 read-write GPIO8 GPIO8 Original Interrupt Status 8 1 read-write GPIO9 GPIO9 Original Interrupt Status 9 1 read-write VERSION GPIO VERSION 0xC00 32 read-only n 0xD6610 0xFFFFFFFF PC PA P0RT 0x40002000 0x0 0x1000 registers n PC PC Interrupt 18 CFG0 PORT Control Register 0x0 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG1 PORT Control Register 0x4 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG10 PORT Control Register 0x28 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG11 PORT Control Register 0x2C 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG12 PORT Control Register 0x30 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG13 PORT Control Register 0x34 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG14 PORT Control Register 0x38 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG15 PORT Control Register 0x3C 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG2 PORT Control Register 0x8 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG3 PORT Control Register 0xC 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG4 PORT Control Register 0x10 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG5 PORT Control Register 0x14 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG6 PORT Control Register 0x18 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG7 PORT Control Register 0x1C 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG8 PORT Control Register 0x20 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG9 PORT Control Register 0x24 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write GCFG0 Global Configuration Register 0 0xD8 32 write-only n 0x0 0xFFFFFFFF GMASK0 GMASK0 0 1 write-only GMASK1 GMASK1 1 1 write-only GMASK10 GMASK10 10 1 write-only GMASK11 GMASK11 11 1 write-only GMASK12 GMASK12 12 1 write-only GMASK13 GMASK13 13 1 write-only GMASK14 GMASK14 14 1 write-only GMASK15 GMASK15 15 1 write-only GMASK16 GMASK16 16 1 write-only GMASK17 GMASK17 17 1 write-only GMASK18 GMASK18 18 1 write-only GMASK19 GMASK19 19 1 write-only GMASK2 GMASK2 2 1 write-only GMASK20 GMASK20 20 1 write-only GMASK21 GMASK21 21 1 write-only GMASK22 GMASK22 22 1 write-only GMASK23 GMASK23 23 1 write-only GMASK24 GMASK24 24 1 write-only GMASK25 GMASK25 25 1 write-only GMASK26 GMASK26 26 1 write-only GMASK27 GMASK27 27 1 write-only GMASK28 GMASK28 28 1 write-only GMASK29 GMASK29 29 1 write-only GMASK3 GMASK3 3 1 write-only GMASK30 GMASK30 30 1 write-only GMASK31 GMASK31 31 1 write-only GMASK4 GMASK4 4 1 write-only GMASK5 GMASK5 5 1 write-only GMASK6 GMASK6 6 1 write-only GMASK7 GMASK7 7 1 write-only GMASK8 GMASK8 8 1 write-only GMASK9 GMASK9 9 1 write-only GCFG1 0xDC -1 read-write n GCFGMASK GLOBAL CONFIGUE MASK REGISTER 0xD0 32 read-write n 0xFFFFFFFF 0x0 GMASK0 GMASK0 0 1 read-write GMASK1 GMASK1 1 1 read-write GMASK10 GMASK10 10 1 read-write GMASK11 GMASK11 11 1 read-write GMASK12 GMASK12 12 1 read-write GMASK13 GMASK13 13 1 read-write GMASK14 GMASK14 14 1 read-write GMASK15 GMASK15 15 1 read-write GMASK16 GMASK16 16 1 read-write GMASK17 GMASK17 17 1 read-write GMASK18 GMASK18 18 1 read-write GMASK19 GMASK19 19 1 read-write GMASK2 GMASK2 2 1 read-write GMASK20 GMASK20 20 1 read-write GMASK21 GMASK21 21 1 read-write GMASK22 GMASK22 22 1 read-write GMASK23 GMASK23 23 1 read-write GMASK24 GMASK24 24 1 read-write GMASK25 GMASK25 25 1 read-write GMASK26 GMASK26 26 1 read-write GMASK27 GMASK27 27 1 read-write GMASK28 GMASK28 28 1 read-write GMASK29 GMASK29 29 1 read-write GMASK3 GMASK3 3 1 read-write GMASK30 GMASK30 30 1 read-write GMASK31 GMASK31 31 1 read-write GMASK4 GMASK4 4 1 read-write GMASK5 GMASK5 5 1 read-write GMASK6 GMASK6 6 1 read-write GMASK7 GMASK7 7 1 read-write GMASK8 GMASK8 8 1 read-write GMASK9 GMASK9 9 1 read-write INTBV Interrupt Double Edge Register 0xB8 32 read-write n 0x0 0xFFFFFFFF GPIO0 GPIO0 Bipolar Interrupt Enable 0 1 read-write GPIO1 GPIO1 Bipolar Interrupt Enable 1 1 read-write GPIO10 GPIO10 Bipolar Interrupt Enable 10 1 read-write GPIO11 GPIO11 Bipolar Interrupt Enable 11 1 read-write GPIO12 GPIO12 Bipolar Interrupt Enable 12 1 read-write GPIO13 GPIO13 Bipolar Interrupt Enable 13 1 read-write GPIO14 GPIO14 Bipolar Interrupt Enable 14 1 read-write GPIO15 GPIO15 Bipolar Interrupt Enable 15 1 read-write GPIO2 GPIO2 Bipolar Interrupt Enable 2 1 read-write GPIO3 GPIO3 Bipolar Interrupt Enable 3 1 read-write GPIO4 GPIO4 Bipolar Interrupt Enable 4 1 read-write GPIO5 GPIO5 Bipolar Interrupt Enable 5 1 read-write GPIO6 GPIO6 Bipolar Interrupt Enable 6 1 read-write GPIO7 GPIO7 Bipolar Interrupt Enable 7 1 read-write GPIO8 GPIO8 Bipolar Interrupt Enable 8 1 read-write GPIO9 GPIO9 Bipolar Interrupt Enable 9 1 read-write INTMASK Interrupt Mask Register 0xB0 32 read-write n 0xFFFFFFFF 0xFFFFFFFF GPIO0 GPIO0 Interrupt Mask 0 1 read-write GPIO1 GPIO1 Interrupt Mask 1 1 read-write GPIO10 GPIO10 Interrupt Mask 10 1 read-write GPIO11 GPIO11 Interrupt Mask 11 1 read-write GPIO12 GPIO12 Interrupt Mask 12 1 read-write GPIO13 GPIO13 Interrupt Mask 13 1 read-write GPIO14 GPIO14 Interrupt Mask 14 1 read-write GPIO15 GPIO15 Interrupt Mask 15 1 read-write GPIO2 GPIO2 Interrupt Mask 2 1 read-write GPIO3 GPIO3 Interrupt Mask 3 1 read-write GPIO4 GPIO4 Interrupt Mask 4 1 read-write GPIO5 GPIO5 Interrupt Mask 5 1 read-write GPIO6 GPIO6 Interrupt Mask 6 1 read-write GPIO7 GPIO7 Interrupt Mask 7 1 read-write GPIO8 GPIO8 Interrupt Mask 8 1 read-write GPIO9 GPIO9 Interrupt Mask 9 1 read-write INTPOL Interrupt Polarity Register 0xBC 32 read-write n 0x0 0xFFFFFFFF GPIO0 GPIO0 Interrupt Polarity Enable 0 1 read-write GPIO1 GPIO1 Interrupt Polarity Enable 1 1 read-write GPIO10 GPIO10 Interrupt Polarity Enable 10 1 read-write GPIO11 GPIO11 Interrupt Polarity Enable 11 1 read-write GPIO12 GPIO12 Interrupt Polarity Enable 12 1 read-write GPIO13 GPIO13 Interrupt Polarity Enable 13 1 read-write GPIO14 GPIO14 Interrupt Polarity Enable 14 1 read-write GPIO15 GPIO15 Interrupt Polarity Enable 15 1 read-write GPIO2 GPIO2 Interrupt Polarity Enable 2 1 read-write GPIO3 GPIO3 Interrupt Polarity Enable 3 1 read-write GPIO4 GPIO4 Interrupt Polarity Enable 4 1 read-write GPIO5 GPIO5 Interrupt Polarity Enable 5 1 read-write GPIO6 GPIO6 Interrupt Polarity Enable 6 1 read-write GPIO7 GPIO7 Interrupt Polarity Enable 7 1 read-write GPIO8 GPIO8 Interrupt Polarity Enable 8 1 read-write GPIO9 GPIO9 Interrupt Polarity Enable 9 1 read-write INTTYPE Interrupt Type Register 0xB4 32 read-write n 0x0 0xFFFFFFFF GPIO0 GPIO0 Interrupt Type Select 0 1 read-write GPIO1 GPIO1 Interrupt Type Select 1 1 read-write GPIO10 GPIO10 Interrupt Type Select 10 1 read-write GPIO11 GPIO11 Interrupt Type Select 11 1 read-write GPIO12 GPIO12 Interrupt Type Select 12 1 read-write GPIO13 GPIO13 Interrupt Type Select 13 1 read-write GPIO14 GPIO14 Interrupt Type Select 14 1 read-write GPIO15 GPIO15 Interrupt Type Select 15 1 read-write GPIO2 GPIO2 Interrupt Type Select 2 1 read-write GPIO3 GPIO3 Interrupt Type Select 3 1 read-write GPIO4 GPIO4 Interrupt Type Select 4 1 read-write GPIO5 GPIO5 Interrupt Type Select 5 1 read-write GPIO6 GPIO6 Interrupt Type Select 6 1 read-write GPIO7 GPIO7 Interrupt Type Select 7 1 read-write GPIO8 GPIO8 Interrupt Type Select 8 1 read-write GPIO9 GPIO9 Interrupt Type Select 9 1 read-write LOCK0 Configure LOCK Register 0 0xE0 32 read-write n 0x0 0xFFFFFFFF LOCKL0 LOCKL0 0 1 read-write LOCKL1 LOCKL1 1 1 read-write LOCKL10 LOCKL10 10 1 read-write LOCKL11 LOCKL11 11 1 read-write LOCKL12 LOCKL12 12 1 read-write LOCKL13 LOCKL13 13 1 read-write LOCKL14 LOCKL14 14 1 read-write LOCKL15 LOCKL15 15 1 read-write LOCKL2 LOCKL2 2 1 read-write LOCKL3 LOCKL3 3 1 read-write LOCKL4 LOCKL4 4 1 read-write LOCKL5 LOCKL5 5 1 read-write LOCKL6 LOCKL6 6 1 read-write LOCKL7 LOCKL7 7 1 read-write LOCKL8 LOCKL8 8 1 read-write LOCKL9 LOCKL9 9 1 read-write LOCKL_KEY LOCKL_KEY 16 16 read-write LOCK1 0xE4 -1 read-write n MIS Mask Interrupt Status Register 0xC4 32 read-write n 0x0 0xFFFFFFFF GPIO0 GPIO0 Masked Interrupt Status 0 1 read-write GPIO1 GPIO1 Masked Interrupt Status 1 1 read-write GPIO10 GPIO10 Masked Interrupt Status 10 1 read-write GPIO11 GPIO11 Masked Interrupt Status 11 1 read-write GPIO12 GPIO12 Masked Interrupt Status 12 1 read-write GPIO13 GPIO13 Masked Interrupt Status 13 1 read-write GPIO14 GPIO14 Masked Interrupt Status 14 1 read-write GPIO15 GPIO15 Masked Interrupt Status 15 1 read-write GPIO2 GPIO2 Masked Interrupt Status 2 1 read-write GPIO3 GPIO3 Masked Interrupt Status 3 1 read-write GPIO4 GPIO4 Masked Interrupt Status 4 1 read-write GPIO5 GPIO5 Masked Interrupt Status 5 1 read-write GPIO6 GPIO6 Masked Interrupt Status 6 1 read-write GPIO7 GPIO7 Masked Interrupt Status 7 1 read-write GPIO8 GPIO8 Masked Interrupt Status 8 1 read-write GPIO9 GPIO9 Masked Interrupt Status 9 1 read-write OUT Pin Output Register 0x90 32 read-write n 0x0 0xFFFFFFFF GPIO0 GPIO0 Output Status 0 1 read-write GPIO1 GPIO1 Output Status 1 1 read-write GPIO10 GPIO10 Output Status 10 1 read-write GPIO11 GPIO11 Output Status 11 1 read-write GPIO12 GPIO12 Output Status 12 1 read-write GPIO13 GPIO13 Output Status 13 1 read-write GPIO14 GPIO14 Output Status 14 1 read-write GPIO15 GPIO15 Output Status 15 1 read-write GPIO2 GPIO2 Output Status 2 1 read-write GPIO3 GPIO3 Output Status 3 1 read-write GPIO4 GPIO4 Output Status 4 1 read-write GPIO5 GPIO5 Output Status 5 1 read-write GPIO6 GPIO6 Output Status 6 1 read-write GPIO7 GPIO7 Output Status 7 1 read-write GPIO8 GPIO8 Output Status 8 1 read-write GPIO9 GPIO9 Output Status 9 1 read-write OUTCLR Pin Output Clear Register 0x98 32 read-write n 0x0 0xFFFFFFFF GPIO0 GPIO0 Output Clear 0 1 read-write GPIO1 GPIO1 Output Clear 1 1 read-write GPIO10 GPIO10 Output Clear 10 1 read-write GPIO11 GPIO11 Output Clear 11 1 read-write GPIO12 GPIO12 Output Clear 12 1 read-write GPIO13 GPIO13 Output Clear 13 1 read-write GPIO14 GPIO14 Output Clear 14 1 read-write GPIO15 GPIO15 Output Clear 15 1 read-write GPIO2 GPIO2 Output Clear 2 1 read-write GPIO3 GPIO3 Output Clear 3 1 read-write GPIO4 GPIO4 Output Clear 4 1 read-write GPIO5 GPIO5 Output Clear 5 1 read-write GPIO6 GPIO6 Output Clear 6 1 read-write GPIO7 GPIO7 Output Clear 7 1 read-write GPIO8 GPIO8 Output Clear 8 1 read-write GPIO9 GPIO9 Output Clear 9 1 read-write OUTEN Pin Output Enable Register 0xA0 32 read-write n 0x0 0xFFFFFFFF GPIO0 GPIO0 Output Enable 0 1 read-write GPIO1 GPIO1 Output Enable 1 1 read-write GPIO10 GPIO10 Output Enable 10 1 read-write GPIO11 GPIO11 Output Enable 11 1 read-write GPIO12 GPIO12 Output Enable 12 1 read-write GPIO13 GPIO13 Output Enable 13 1 read-write GPIO14 GPIO14 Output Enable 14 1 read-write GPIO15 GPIO15 Output Enable 15 1 read-write GPIO2 GPIO2 Output Enable 2 1 read-write GPIO3 GPIO3 Output Enable 3 1 read-write GPIO4 GPIO4 Output Enable 4 1 read-write GPIO5 GPIO5 Output Enable 5 1 read-write GPIO6 GPIO6 Output Enable 6 1 read-write GPIO7 GPIO7 Output Enable 7 1 read-write GPIO8 GPIO8 Output Enable 8 1 read-write GPIO9 GPIO9 Output Enable 9 1 read-write OUTSET Pin Output Set Register 0x94 32 read-write n 0x0 0xFFFFFFFF GPIO0 GPIO0 Output Set 0 1 read-write GPIO1 GPIO1 Output Set 1 1 read-write GPIO10 GPIO10 Output Set 10 1 read-write GPIO11 GPIO11 Output Set 11 1 read-write GPIO12 GPIO12 Output Set 12 1 read-write GPIO13 GPIO13 Output Set 13 1 read-write GPIO14 GPIO14 Output Set 14 1 read-write GPIO15 GPIO15 Output Set 15 1 read-write GPIO2 GPIO2 Output Set 2 1 read-write GPIO3 GPIO3 Output Set 3 1 read-write GPIO4 GPIO4 Output Set 4 1 read-write GPIO5 GPIO5 Output Set 5 1 read-write GPIO6 GPIO6 Output Set 6 1 read-write GPIO7 GPIO7 Output Set 7 1 read-write GPIO8 GPIO8 Output Set 8 1 read-write GPIO9 GPIO9 Output Set 9 1 read-write OUTTGL Pin Output Turn Register 0x9C 32 read-write n 0x0 0xFFFFFFFF GPIO0 GPIO0 Output Toggle 0 1 read-write GPIO1 GPIO1 Output Toggle 1 1 read-write GPIO10 GPIO10 Output Toggle 10 1 read-write GPIO11 GPIO11 Output Toggle 11 1 read-write GPIO12 GPIO12 Output Toggle 12 1 read-write GPIO13 GPIO13 Output Toggle 13 1 read-write GPIO14 GPIO14 Output Toggle 14 1 read-write GPIO15 GPIO15 Output Toggle 15 1 read-write GPIO2 GPIO2 Output Toggle 2 1 read-write GPIO3 GPIO3 Output Toggle 3 1 read-write GPIO4 GPIO4 Output Toggle 4 1 read-write GPIO5 GPIO5 Output Toggle 5 1 read-write GPIO6 GPIO6 Output Toggle 6 1 read-write GPIO7 GPIO7 Output Toggle 7 1 read-write GPIO8 GPIO8 Output Toggle 8 1 read-write GPIO9 GPIO9 Output Toggle 9 1 read-write PIN Pin Value Register 0x80 32 read-only n 0x0 0xFFFFFFFF GPIO0 GPIO0 Status 0 1 read-only GPIO1 GPIO1 Status 1 1 read-only GPIO10 GPIO10 Status 10 1 read-only GPIO11 GPIO11 Status 11 1 read-only GPIO12 GPIO12 Status 12 1 read-only GPIO13 GPIO13 Status 13 1 read-only GPIO14 GPIO14 Status 14 1 read-only GPIO15 GPIO15 Status 15 1 read-only GPIO2 GPIO2 Status 2 1 read-only GPIO3 GPIO3 Status 3 1 read-only GPIO4 GPIO4 Status 4 1 read-only GPIO5 GPIO5 Status 5 1 read-only GPIO6 GPIO6 Status 6 1 read-only GPIO7 GPIO7 Status 7 1 read-only GPIO8 GPIO8 Status 8 1 read-only GPIO9 GPIO9 Status 9 1 read-only RIS Original Interrupt Status Register 0xC0 32 read-write n 0x0 0xFFFFFFFF GPIO0 GPIO0 Original Interrupt Status 0 1 read-write GPIO1 GPIO1 Original Interrupt Status 1 1 read-write GPIO10 GPIO10 Original Interrupt Status 10 1 read-write GPIO11 GPIO11 Original Interrupt Status 11 1 read-write GPIO12 GPIO12 Original Interrupt Status 12 1 read-write GPIO13 GPIO13 Original Interrupt Status 13 1 read-write GPIO14 GPIO14 Original Interrupt Status 14 1 read-write GPIO15 GPIO15 Original Interrupt Status 15 1 read-write GPIO2 GPIO2 Original Interrupt Status 2 1 read-write GPIO3 GPIO3 Original Interrupt Status 3 1 read-write GPIO4 GPIO4 Original Interrupt Status 4 1 read-write GPIO5 GPIO5 Original Interrupt Status 5 1 read-write GPIO6 GPIO6 Original Interrupt Status 6 1 read-write GPIO7 GPIO7 Original Interrupt Status 7 1 read-write GPIO8 GPIO8 Original Interrupt Status 8 1 read-write GPIO9 GPIO9 Original Interrupt Status 9 1 read-write VERSION GPIO VERSION 0xC00 32 read-only n 0xD6610 0xFFFFFFFF PF PA P0RT 0x40005000 0x0 0x1000 registers n PF PF Interrupt 19 CFG0 PORT Control Register 0x0 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG1 PORT Control Register 0x4 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG10 PORT Control Register 0x28 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG11 PORT Control Register 0x2C 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG12 PORT Control Register 0x30 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG13 PORT Control Register 0x34 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG14 PORT Control Register 0x38 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG15 PORT Control Register 0x3C 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG2 PORT Control Register 0x8 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG3 PORT Control Register 0xC 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG4 PORT Control Register 0x10 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG5 PORT Control Register 0x14 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG6 PORT Control Register 0x18 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG7 PORT Control Register 0x1C 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG8 PORT Control Register 0x20 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG9 PORT Control Register 0x24 32 read-write n 0x0 0xFFFFFFFF AEN AEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write GCFG0 Global Configuration Register 0 0xD8 32 write-only n 0x0 0xFFFFFFFF GMASK0 GMASK0 0 1 write-only GMASK1 GMASK1 1 1 write-only GMASK10 GMASK10 10 1 write-only GMASK11 GMASK11 11 1 write-only GMASK12 GMASK12 12 1 write-only GMASK13 GMASK13 13 1 write-only GMASK14 GMASK14 14 1 write-only GMASK15 GMASK15 15 1 write-only GMASK16 GMASK16 16 1 write-only GMASK17 GMASK17 17 1 write-only GMASK18 GMASK18 18 1 write-only GMASK19 GMASK19 19 1 write-only GMASK2 GMASK2 2 1 write-only GMASK20 GMASK20 20 1 write-only GMASK21 GMASK21 21 1 write-only GMASK22 GMASK22 22 1 write-only GMASK23 GMASK23 23 1 write-only GMASK24 GMASK24 24 1 write-only GMASK25 GMASK25 25 1 write-only GMASK26 GMASK26 26 1 write-only GMASK27 GMASK27 27 1 write-only GMASK28 GMASK28 28 1 write-only GMASK29 GMASK29 29 1 write-only GMASK3 GMASK3 3 1 write-only GMASK30 GMASK30 30 1 write-only GMASK31 GMASK31 31 1 write-only GMASK4 GMASK4 4 1 write-only GMASK5 GMASK5 5 1 write-only GMASK6 GMASK6 6 1 write-only GMASK7 GMASK7 7 1 write-only GMASK8 GMASK8 8 1 write-only GMASK9 GMASK9 9 1 write-only GCFG1 0xDC -1 read-write n GCFGMASK GLOBAL CONFIGUE MASK REGISTER 0xD0 32 read-write n 0xFFFFFFFF 0x0 GMASK0 GMASK0 0 1 read-write GMASK1 GMASK1 1 1 read-write GMASK10 GMASK10 10 1 read-write GMASK11 GMASK11 11 1 read-write GMASK12 GMASK12 12 1 read-write GMASK13 GMASK13 13 1 read-write GMASK14 GMASK14 14 1 read-write GMASK15 GMASK15 15 1 read-write GMASK16 GMASK16 16 1 read-write GMASK17 GMASK17 17 1 read-write GMASK18 GMASK18 18 1 read-write GMASK19 GMASK19 19 1 read-write GMASK2 GMASK2 2 1 read-write GMASK20 GMASK20 20 1 read-write GMASK21 GMASK21 21 1 read-write GMASK22 GMASK22 22 1 read-write GMASK23 GMASK23 23 1 read-write GMASK24 GMASK24 24 1 read-write GMASK25 GMASK25 25 1 read-write GMASK26 GMASK26 26 1 read-write GMASK27 GMASK27 27 1 read-write GMASK28 GMASK28 28 1 read-write GMASK29 GMASK29 29 1 read-write GMASK3 GMASK3 3 1 read-write GMASK30 GMASK30 30 1 read-write GMASK31 GMASK31 31 1 read-write GMASK4 GMASK4 4 1 read-write GMASK5 GMASK5 5 1 read-write GMASK6 GMASK6 6 1 read-write GMASK7 GMASK7 7 1 read-write GMASK8 GMASK8 8 1 read-write GMASK9 GMASK9 9 1 read-write INTBV Interrupt Double Edge Register 0xB8 32 read-write n 0x0 0xFFFFFFFF GPIO0 GPIO0 Bipolar Interrupt Enable 0 1 read-write GPIO1 GPIO1 Bipolar Interrupt Enable 1 1 read-write GPIO10 GPIO10 Bipolar Interrupt Enable 10 1 read-write GPIO11 GPIO11 Bipolar Interrupt Enable 11 1 read-write GPIO12 GPIO12 Bipolar Interrupt Enable 12 1 read-write GPIO13 GPIO13 Bipolar Interrupt Enable 13 1 read-write GPIO14 GPIO14 Bipolar Interrupt Enable 14 1 read-write GPIO15 GPIO15 Bipolar Interrupt Enable 15 1 read-write GPIO2 GPIO2 Bipolar Interrupt Enable 2 1 read-write GPIO3 GPIO3 Bipolar Interrupt Enable 3 1 read-write GPIO4 GPIO4 Bipolar Interrupt Enable 4 1 read-write GPIO5 GPIO5 Bipolar Interrupt Enable 5 1 read-write GPIO6 GPIO6 Bipolar Interrupt Enable 6 1 read-write GPIO7 GPIO7 Bipolar Interrupt Enable 7 1 read-write GPIO8 GPIO8 Bipolar Interrupt Enable 8 1 read-write GPIO9 GPIO9 Bipolar Interrupt Enable 9 1 read-write INTMASK Interrupt Mask Register 0xB0 32 read-write n 0xFFFFFFFF 0xFFFFFFFF GPIO0 GPIO0 Interrupt Mask 0 1 read-write GPIO1 GPIO1 Interrupt Mask 1 1 read-write GPIO10 GPIO10 Interrupt Mask 10 1 read-write GPIO11 GPIO11 Interrupt Mask 11 1 read-write GPIO12 GPIO12 Interrupt Mask 12 1 read-write GPIO13 GPIO13 Interrupt Mask 13 1 read-write GPIO14 GPIO14 Interrupt Mask 14 1 read-write GPIO15 GPIO15 Interrupt Mask 15 1 read-write GPIO2 GPIO2 Interrupt Mask 2 1 read-write GPIO3 GPIO3 Interrupt Mask 3 1 read-write GPIO4 GPIO4 Interrupt Mask 4 1 read-write GPIO5 GPIO5 Interrupt Mask 5 1 read-write GPIO6 GPIO6 Interrupt Mask 6 1 read-write GPIO7 GPIO7 Interrupt Mask 7 1 read-write GPIO8 GPIO8 Interrupt Mask 8 1 read-write GPIO9 GPIO9 Interrupt Mask 9 1 read-write INTPOL Interrupt Polarity Register 0xBC 32 read-write n 0x0 0xFFFFFFFF GPIO0 GPIO0 Interrupt Polarity Enable 0 1 read-write GPIO1 GPIO1 Interrupt Polarity Enable 1 1 read-write GPIO10 GPIO10 Interrupt Polarity Enable 10 1 read-write GPIO11 GPIO11 Interrupt Polarity Enable 11 1 read-write GPIO12 GPIO12 Interrupt Polarity Enable 12 1 read-write GPIO13 GPIO13 Interrupt Polarity Enable 13 1 read-write GPIO14 GPIO14 Interrupt Polarity Enable 14 1 read-write GPIO15 GPIO15 Interrupt Polarity Enable 15 1 read-write GPIO2 GPIO2 Interrupt Polarity Enable 2 1 read-write GPIO3 GPIO3 Interrupt Polarity Enable 3 1 read-write GPIO4 GPIO4 Interrupt Polarity Enable 4 1 read-write GPIO5 GPIO5 Interrupt Polarity Enable 5 1 read-write GPIO6 GPIO6 Interrupt Polarity Enable 6 1 read-write GPIO7 GPIO7 Interrupt Polarity Enable 7 1 read-write GPIO8 GPIO8 Interrupt Polarity Enable 8 1 read-write GPIO9 GPIO9 Interrupt Polarity Enable 9 1 read-write INTTYPE Interrupt Type Register 0xB4 32 read-write n 0x0 0xFFFFFFFF GPIO0 GPIO0 Interrupt Type Select 0 1 read-write GPIO1 GPIO1 Interrupt Type Select 1 1 read-write GPIO10 GPIO10 Interrupt Type Select 10 1 read-write GPIO11 GPIO11 Interrupt Type Select 11 1 read-write GPIO12 GPIO12 Interrupt Type Select 12 1 read-write GPIO13 GPIO13 Interrupt Type Select 13 1 read-write GPIO14 GPIO14 Interrupt Type Select 14 1 read-write GPIO15 GPIO15 Interrupt Type Select 15 1 read-write GPIO2 GPIO2 Interrupt Type Select 2 1 read-write GPIO3 GPIO3 Interrupt Type Select 3 1 read-write GPIO4 GPIO4 Interrupt Type Select 4 1 read-write GPIO5 GPIO5 Interrupt Type Select 5 1 read-write GPIO6 GPIO6 Interrupt Type Select 6 1 read-write GPIO7 GPIO7 Interrupt Type Select 7 1 read-write GPIO8 GPIO8 Interrupt Type Select 8 1 read-write GPIO9 GPIO9 Interrupt Type Select 9 1 read-write LOCK0 Configure LOCK Register 0 0xE0 32 read-write n 0x0 0xFFFFFFFF LOCKL0 LOCKL0 0 1 read-write LOCKL1 LOCKL1 1 1 read-write LOCKL10 LOCKL10 10 1 read-write LOCKL11 LOCKL11 11 1 read-write LOCKL12 LOCKL12 12 1 read-write LOCKL13 LOCKL13 13 1 read-write LOCKL14 LOCKL14 14 1 read-write LOCKL15 LOCKL15 15 1 read-write LOCKL2 LOCKL2 2 1 read-write LOCKL3 LOCKL3 3 1 read-write LOCKL4 LOCKL4 4 1 read-write LOCKL5 LOCKL5 5 1 read-write LOCKL6 LOCKL6 6 1 read-write LOCKL7 LOCKL7 7 1 read-write LOCKL8 LOCKL8 8 1 read-write LOCKL9 LOCKL9 9 1 read-write LOCKL_KEY LOCKL_KEY 16 16 read-write LOCK1 0xE4 -1 read-write n MIS Mask Interrupt Status Register 0xC4 32 read-write n 0x0 0xFFFFFFFF GPIO0 GPIO0 Masked Interrupt Status 0 1 read-write GPIO1 GPIO1 Masked Interrupt Status 1 1 read-write GPIO10 GPIO10 Masked Interrupt Status 10 1 read-write GPIO11 GPIO11 Masked Interrupt Status 11 1 read-write GPIO12 GPIO12 Masked Interrupt Status 12 1 read-write GPIO13 GPIO13 Masked Interrupt Status 13 1 read-write GPIO14 GPIO14 Masked Interrupt Status 14 1 read-write GPIO15 GPIO15 Masked Interrupt Status 15 1 read-write GPIO2 GPIO2 Masked Interrupt Status 2 1 read-write GPIO3 GPIO3 Masked Interrupt Status 3 1 read-write GPIO4 GPIO4 Masked Interrupt Status 4 1 read-write GPIO5 GPIO5 Masked Interrupt Status 5 1 read-write GPIO6 GPIO6 Masked Interrupt Status 6 1 read-write GPIO7 GPIO7 Masked Interrupt Status 7 1 read-write GPIO8 GPIO8 Masked Interrupt Status 8 1 read-write GPIO9 GPIO9 Masked Interrupt Status 9 1 read-write OUT Pin Output Register 0x90 32 read-write n 0x0 0xFFFFFFFF GPIO0 GPIO0 Output Status 0 1 read-write GPIO1 GPIO1 Output Status 1 1 read-write GPIO10 GPIO10 Output Status 10 1 read-write GPIO11 GPIO11 Output Status 11 1 read-write GPIO12 GPIO12 Output Status 12 1 read-write GPIO13 GPIO13 Output Status 13 1 read-write GPIO14 GPIO14 Output Status 14 1 read-write GPIO15 GPIO15 Output Status 15 1 read-write GPIO2 GPIO2 Output Status 2 1 read-write GPIO3 GPIO3 Output Status 3 1 read-write GPIO4 GPIO4 Output Status 4 1 read-write GPIO5 GPIO5 Output Status 5 1 read-write GPIO6 GPIO6 Output Status 6 1 read-write GPIO7 GPIO7 Output Status 7 1 read-write GPIO8 GPIO8 Output Status 8 1 read-write GPIO9 GPIO9 Output Status 9 1 read-write OUTCLR Pin Output Clear Register 0x98 32 read-write n 0x0 0xFFFFFFFF GPIO0 GPIO0 Output Clear 0 1 read-write GPIO1 GPIO1 Output Clear 1 1 read-write GPIO10 GPIO10 Output Clear 10 1 read-write GPIO11 GPIO11 Output Clear 11 1 read-write GPIO12 GPIO12 Output Clear 12 1 read-write GPIO13 GPIO13 Output Clear 13 1 read-write GPIO14 GPIO14 Output Clear 14 1 read-write GPIO15 GPIO15 Output Clear 15 1 read-write GPIO2 GPIO2 Output Clear 2 1 read-write GPIO3 GPIO3 Output Clear 3 1 read-write GPIO4 GPIO4 Output Clear 4 1 read-write GPIO5 GPIO5 Output Clear 5 1 read-write GPIO6 GPIO6 Output Clear 6 1 read-write GPIO7 GPIO7 Output Clear 7 1 read-write GPIO8 GPIO8 Output Clear 8 1 read-write GPIO9 GPIO9 Output Clear 9 1 read-write OUTEN Pin Output Enable Register 0xA0 32 read-write n 0x0 0xFFFFFFFF GPIO0 GPIO0 Output Enable 0 1 read-write GPIO1 GPIO1 Output Enable 1 1 read-write GPIO10 GPIO10 Output Enable 10 1 read-write GPIO11 GPIO11 Output Enable 11 1 read-write GPIO12 GPIO12 Output Enable 12 1 read-write GPIO13 GPIO13 Output Enable 13 1 read-write GPIO14 GPIO14 Output Enable 14 1 read-write GPIO15 GPIO15 Output Enable 15 1 read-write GPIO2 GPIO2 Output Enable 2 1 read-write GPIO3 GPIO3 Output Enable 3 1 read-write GPIO4 GPIO4 Output Enable 4 1 read-write GPIO5 GPIO5 Output Enable 5 1 read-write GPIO6 GPIO6 Output Enable 6 1 read-write GPIO7 GPIO7 Output Enable 7 1 read-write GPIO8 GPIO8 Output Enable 8 1 read-write GPIO9 GPIO9 Output Enable 9 1 read-write OUTSET Pin Output Set Register 0x94 32 read-write n 0x0 0xFFFFFFFF GPIO0 GPIO0 Output Set 0 1 read-write GPIO1 GPIO1 Output Set 1 1 read-write GPIO10 GPIO10 Output Set 10 1 read-write GPIO11 GPIO11 Output Set 11 1 read-write GPIO12 GPIO12 Output Set 12 1 read-write GPIO13 GPIO13 Output Set 13 1 read-write GPIO14 GPIO14 Output Set 14 1 read-write GPIO15 GPIO15 Output Set 15 1 read-write GPIO2 GPIO2 Output Set 2 1 read-write GPIO3 GPIO3 Output Set 3 1 read-write GPIO4 GPIO4 Output Set 4 1 read-write GPIO5 GPIO5 Output Set 5 1 read-write GPIO6 GPIO6 Output Set 6 1 read-write GPIO7 GPIO7 Output Set 7 1 read-write GPIO8 GPIO8 Output Set 8 1 read-write GPIO9 GPIO9 Output Set 9 1 read-write OUTTGL Pin Output Turn Register 0x9C 32 read-write n 0x0 0xFFFFFFFF GPIO0 GPIO0 Output Toggle 0 1 read-write GPIO1 GPIO1 Output Toggle 1 1 read-write GPIO10 GPIO10 Output Toggle 10 1 read-write GPIO11 GPIO11 Output Toggle 11 1 read-write GPIO12 GPIO12 Output Toggle 12 1 read-write GPIO13 GPIO13 Output Toggle 13 1 read-write GPIO14 GPIO14 Output Toggle 14 1 read-write GPIO15 GPIO15 Output Toggle 15 1 read-write GPIO2 GPIO2 Output Toggle 2 1 read-write GPIO3 GPIO3 Output Toggle 3 1 read-write GPIO4 GPIO4 Output Toggle 4 1 read-write GPIO5 GPIO5 Output Toggle 5 1 read-write GPIO6 GPIO6 Output Toggle 6 1 read-write GPIO7 GPIO7 Output Toggle 7 1 read-write GPIO8 GPIO8 Output Toggle 8 1 read-write GPIO9 GPIO9 Output Toggle 9 1 read-write PIN Pin Value Register 0x80 32 read-only n 0x0 0xFFFFFFFF GPIO0 GPIO0 Status 0 1 read-only GPIO1 GPIO1 Status 1 1 read-only GPIO10 GPIO10 Status 10 1 read-only GPIO11 GPIO11 Status 11 1 read-only GPIO12 GPIO12 Status 12 1 read-only GPIO13 GPIO13 Status 13 1 read-only GPIO14 GPIO14 Status 14 1 read-only GPIO15 GPIO15 Status 15 1 read-only GPIO2 GPIO2 Status 2 1 read-only GPIO3 GPIO3 Status 3 1 read-only GPIO4 GPIO4 Status 4 1 read-only GPIO5 GPIO5 Status 5 1 read-only GPIO6 GPIO6 Status 6 1 read-only GPIO7 GPIO7 Status 7 1 read-only GPIO8 GPIO8 Status 8 1 read-only GPIO9 GPIO9 Status 9 1 read-only RIS Original Interrupt Status Register 0xC0 32 read-write n 0x0 0xFFFFFFFF GPIO0 GPIO0 Original Interrupt Status 0 1 read-write GPIO1 GPIO1 Original Interrupt Status 1 1 read-write GPIO10 GPIO10 Original Interrupt Status 10 1 read-write GPIO11 GPIO11 Original Interrupt Status 11 1 read-write GPIO12 GPIO12 Original Interrupt Status 12 1 read-write GPIO13 GPIO13 Original Interrupt Status 13 1 read-write GPIO14 GPIO14 Original Interrupt Status 14 1 read-write GPIO15 GPIO15 Original Interrupt Status 15 1 read-write GPIO2 GPIO2 Original Interrupt Status 2 1 read-write GPIO3 GPIO3 Original Interrupt Status 3 1 read-write GPIO4 GPIO4 Original Interrupt Status 4 1 read-write GPIO5 GPIO5 Original Interrupt Status 5 1 read-write GPIO6 GPIO6 Original Interrupt Status 6 1 read-write GPIO7 GPIO7 Original Interrupt Status 7 1 read-write GPIO8 GPIO8 Original Interrupt Status 8 1 read-write GPIO9 GPIO9 Original Interrupt Status 9 1 read-write VERSION GPIO VERSION 0xC00 32 read-only n 0xD6610 0xFFFFFFFF PPU PPU PPU 0x40082000 0x0 0x100 registers n SYS SYS Interrupt 13 CTRL CTRL Register 0x0 32 read-write n 0x0 0xFFFFFFFF PPU_HPS01_INTR_EN ppu_hps01_intr_en 8 1 read-write PPU_HPS23_INTR_EN ppu_hps23_intr_en 9 1 read-write PPU_PPS01_INTR_EN ppu_pps01_intr_en 12 1 read-write PPU_PPS23_INTR_EN ppu_pps23_intr_en 13 1 read-write PPU_RAM_INTR_EN ppu_ram_intr_en 4 1 read-write HPS01_PROT HPS01_PROT Register 0x20 32 read-write n 0xFFFFFFFF 0xFFFFFFFF PAWEN PA_en 0 1 read-write PBWEN PB_en 1 1 read-write PCWEN PC_en 2 1 read-write PFWEN PF_en 5 1 read-write HPS01_TRAP HPS01_TRAP Register 0x60 32 read-write n 0x0 0xFFFFFFFF PAS PAS 0 1 read-write PBS PBS 1 1 read-write PCS PCS 2 1 read-write PFS PFS 5 1 read-write HPS23_PROT HPS23_PROT Register 0x24 32 read-write n 0xFFFFFFFF 0xFFFFFFFF CRCWEN crc_en 0 1 read-write HPS23_TRAP HPS23_TRAP Register 0x64 32 read-write n 0x0 0xFFFFFFFF CRCS CRCS 0 1 read-write PPS01_PROT PPS01_PROT Register 0x30 32 read-write n 0xFFFFFFFF 0xFFFFFFFF CHIPCWEN chipctrl_en 1 1 read-write DMAWEN dma_en 6 1 read-write EFLASHWEN eflash_en 8 1 read-write ERUWEN eru_en 3 1 read-write I2CWEN i2c_en 23 1 read-write SSPWEN ssp_en 24 1 read-write SYSCWEN syscfg_en 0 1 read-write UART1WEN uart1_en 16 1 read-write UART2WEN uart2_en 17 1 read-write UART3WEN uart3_en 18 1 read-write UART4WEN uart4_en 19 1 read-write UART5WEN uart5_en 20 1 read-write UART6WEN uart6_en 21 1 read-write WDTWEN WDT_en 12 1 read-write PPS01_TRAP PPS01_TRAP Register 0x70 32 read-write n 0x0 0xFFFFFFFF CHIPCS chipctrl_en 1 1 read-write DMAS dma_en 6 1 read-write EFLASHS eflash_en 8 1 read-write ERUS eru_en 3 1 read-write I2CS i2cS 23 1 read-write SSPS sspS 24 1 read-write SYSCS syscfg_en 0 1 read-write UART1S uart1S 16 1 read-write UART2S uart2S 17 1 read-write UART3S uart3S 18 1 read-write UART4S uart4S 19 1 read-write UART5S uart5S 20 1 read-write UART6S uart6S 21 1 read-write WDTS WDT_en 12 1 read-write PPS23_PROT PPS23_PROT Register 0x34 32 read-write n 0xFFFFFFFF 0xFFFFFFFF ACMPWEN acmp_opa_en 10 1 read-write ADCWEN adc_en 8 1 read-write LEDWEN LED_en 14 1 read-write TIM14WEN TIM14_en 0 1 read-write TIM15WEN TIM15_en 1 1 read-write TIM16WEN TIM16_en 2 1 read-write TIM17WEN TIM17_en 3 1 read-write TIM1WEN TIM1_en 12 1 read-write TIM3WEN TIM3_en 13 1 read-write PPS23_TRAP PPS23_PROT Register 0x74 32 read-write n 0x0 0xFFFFFFFF ACMPS acmp_opaS 10 1 read-write ADCS adcS 8 1 read-write LEDS LEDS 14 1 read-write TIM14S TIM14S 0 1 read-write TIM15S TIM15S 1 1 read-write TIM16S TIM16S 2 1 read-write TIM17S TIM17S 3 1 read-write TIM1S TIM1S 12 1 read-write TIM3S TIM3S 13 1 read-write RAM_PROT RAM_PROT Register 0x10 32 read-write n 0xFFFFFFFF 0xFFFFFFFF CRAM0 CRAM0 0 1 read-write CRAM1 CRAM1 1 1 read-write CRAM10 CRAM10 18 1 read-write CRAM11 CRAM11 19 1 read-write CRAM12 CRAM12 20 1 read-write CRAM13 CRAM13 21 1 read-write CRAM14 CRAM14 22 1 read-write CRAM15 CRAM15 23 1 read-write CRAM2 CRAM2 2 1 read-write CRAM3 CRAM3 3 1 read-write CRAM4 CRAM4 4 1 read-write CRAM5 CRAM5 5 1 read-write CRAM6 CRAM6 6 1 read-write CRAM7 CRAM7 7 1 read-write CRAM8 CRAM8 16 1 read-write CRAM9 CRAM9 17 1 read-write DRAM0 DRAM0 8 1 read-write DRAM1 DRAM1 9 1 read-write DRAM10 DRAM10 26 1 read-write DRAM11 DRAM11 27 1 read-write DRAM12 DRAM12 28 1 read-write DRAM13 DRAM13 29 1 read-write DRAM14 DRAM14 30 1 read-write DRAM15 DRAM15 31 1 read-write DRAM2 DRAM2 10 1 read-write DRAM3 DRAM3 11 1 read-write DRAM4 DRAM4 12 1 read-write DRAM5 DRAM5 13 1 read-write DRAM6 DRAM6 14 1 read-write DRAM7 DRAM7 15 1 read-write DRAM8 DRAM8 24 1 read-write DRAM9 DRAM9 25 1 read-write RAM_TRAP RAM_TRAP Register 0x50 32 read-write n 0x0 0xFFFFFFFF CRAM0S CRAM0S 0 1 read-write CRAM10S CRAM10S 18 1 read-write CRAM11S CRAM11S 19 1 read-write CRAM12S CRAM12S 20 1 read-write CRAM13S CRAM13S 21 1 read-write CRAM14S CRAM14S 22 1 read-write CRAM15S CRAM15S 23 1 read-write CRAM1S CRAM1S 1 1 read-write CRAM2S CRAM2S 2 1 read-write CRAM3S CRAM3S 3 1 read-write CRAM4S CRAM4S 4 1 read-write CRAM5S CRAM5S 5 1 read-write CRAM6S CRAM6S 6 1 read-write CRAM7S CRAM7S 7 1 read-write CRAM8S CRAM8S 16 1 read-write CRAM9S CRAM9S 17 1 read-write DRAM0S DRAM0S 8 1 read-write DRAM10S DRAM10S 26 1 read-write DRAM11S DRAM11S 27 1 read-write DRAM12S DRAM12S 28 1 read-write DRAM13S DRAM13S 29 1 read-write DRAM14S DRAM14S 30 1 read-write DRAM15S DRAM15S 31 1 read-write DRAM1S DRAM1S 9 1 read-write DRAM2S DRAM2S 10 1 read-write DRAM3S DRAM3S 11 1 read-write DRAM4S DRAM4S 12 1 read-write DRAM5S DRAM5S 13 1 read-write DRAM6S DRAM6S 14 1 read-write DRAM7S DRAM7S 15 1 read-write DRAM8S DRAM8S 24 1 read-write DRAM9S DRAM9S 25 1 read-write SSP SSP0 module SSP 0x40098000 0x0 0x1000 registers n SSP SSP Interrupt 3 SSPCPSR Clock prescale Register 0x10 32 read-write n 0x0 0xFFFFFFFF CPSDVSR Clock prescale divisor 0 8 read-write SSPCR0 Control Register 0 0x0 32 read-write n 0x0 0xFFFFFFFF DSS Data Size Select 0 4 read-write FRF Frame format 4 2 read-write SCR Serial Clock rate 8 8 read-write SPH SSPCLKOUT phase 7 1 read-write SPO SSPCLKOUT polarity 6 1 read-write SSPCR1 Control Register 1 0x4 32 read-write n 0x0 0xFFFFFFFF LBM Loop back mode 0 1 read-write MS Master or Slave mode select 2 1 read-write SOD Clear Data Overrun 3 1 read-write SSE Synchronous serial port enable 1 1 read-write SSPDMACR DMA Control Register 0x24 32 read-write n 0x0 0xFFFFFFFF RXDMAE Receive DMA Enable. 0 1 read-write TXDMAE Transmit DMA Enable 1 1 read-write SSPDR Data Register 0x8 32 read-write n 0x0 0xFFFFFFFF DATA Transmit/Receive FIFO 0 16 read-write SSPICR Interrupt Clear Register 0x20 32 write-only n 0x0 0xFFFFFFFF RORIC Clears the SSPRORINTR interrupt 0 1 write-only RTIC Clears the SSPRTINTR interrupt 1 1 write-only SSPIMSC Interrupt Set or Clear Register 0x14 32 read-write n 0x0 0xFFFFFFFF RORIM Receive overrun interrupt mask 0 1 read-write RTIM Receive timeout interrupt mask 1 1 read-write RXIM Receive FIFO interrupt mask 2 1 read-write TXIM Receive FIFO interrupt mask 3 1 read-write SSPMIS Masked Interrupt Staus Register 0x1C 32 read-only n 0x0 0xFFFFFFFF RORMIS Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt 0 1 read-only RTMIS Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt 1 1 read-only RXMIS Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt 2 1 read-only TXMIS Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt 3 1 read-only SSPPCID0 PrimCell Identification Register0 0xFF0 32 read-only n 0x0 0xFFFFFFFF SSPPCID1 PrimCell Identification Register1 0xFF4 32 read-only n 0x0 0xFFFFFFFF SSPPCID2 PrimCell Identification Register2 0xFF8 32 read-only n 0x0 0xFFFFFFFF SSPPCID3 PrimCell Identification Register3 0xFFC 32 read-only n 0x0 0xFFFFFFFF SSPPID0 Peripheral Identification Register0 0xFE0 32 read-only n 0x0 0xFFFFFFFF SSPPID1 Peripheral Identification Register1 0xFE4 32 read-only n 0x0 0xFFFFFFFF SSPPID2 Peripheral Identification Register2 0xFE8 32 read-only n 0x0 0xFFFFFFFF SSPPID3 Peripheral Identification Register3 0xFEC 32 read-only n 0x0 0xFFFFFFFF SSPRIS Raw Interrupt Status Register 0x18 32 read-only n 0x0 0xFFFFFFFF RORRIS Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt 0 1 read-only RTRIS Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt 1 1 read-only RXRIS Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt 2 1 read-only TXRIS Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt 3 1 read-only SSPSR Status Register 0xC 32 read-only n 0x0 0xFFFFFFFF BSY PrimeCell SSP busy flag 4 1 read-only RFF Receive FIFO full 3 1 read-only RNE Receive FIFO not empty 2 1 read-only TFE Transmit FIFO emptyt 0 1 read-only TNF Transmit FIFO full 1 1 read-only SYSCFG SYSCFG SYSCFG 0x40080000 0x0 0xD00 registers n ACCESS_EN ACCESS ENABLE Register 0x800 32 read-write n 0x0 0xFFFFFFFF CHIP_ID0 CHIP_ID0 Register 0x130 32 read-only n 0x0 0xFFFFFFFF CHIP_ID1 CHIP_ID1 Register 0x134 32 read-only n 0x0 0xFFFFFFFF CHIP_ID2 CHIP_ID2 Register 0x138 32 read-only n 0x0 0xFFFFFFFF CHIP_ID3 CHIP_ID3 Register 0x13C 32 read-only n 0x0 0xFFFFFFFF ETIMER_CFG ETIMER confige Register 0x14 32 read-write n 0x0 0xFFFFFFFF TIM15_BKIN3 Tim15_bkin3 21 1 read-write TIM15_BKIN_FSEL Tim15_bkin_fsel 20 1 read-write TIM16_BKIN3 Tim16_bkin3 25 1 read-write TIM16_BKIN_FSEL Tim16_bkin_fsel 24 1 read-write TIM17_BKIN3 Tim17_bkin3 29 1 read-write TIM17_BKIN_FSEL Tim17_bkin_fsel 28 1 read-write TIM1_BKIN3 Tim1_bkin3 1 1 read-write TIM1_BKIN_FSEL Tim1_bkin_fsel 0 1 read-write TIM3_BKIN3 Tim3_bkin3 5 1 read-write TIM3_BKIN_FSEL Tim3_bkin_fsel 4 1 read-write MISC_CTRL MISC control Register 0xC 32 read-write n 0x0 0xFFFFFFFF UART3MODE UART3MODE 2 1 read-write SYSINT_STATUS SYSINT status Register 0x100 32 read-only n 0x0 0xFFFFFFFF EFLASH_INTR eflash_intr 1 1 read-only PPU_INTR ppu_intr 0 1 read-only SYSRAM0 sysram0 3 1 read-only SYSRAM0_INTR sysram0_intr 2 1 read-only SYSRAM1 sysram1 5 1 read-only SYSRAM1_INTR sysram1_intr 4 1 read-only SYSRAM_CTRL RAM control Register 0x4 32 read-write n 0x0 0xFFFFFFFF SYSRAM0_PARITY_ERR_CLR sysram0_parity_err_clr 9 1 read-write SYSRAM0_PARITY_INTREN sysram0_parity_intren 8 1 read-write SYSRAM1_PARITY_ERR_CLR sysram1_parity_err_clr 11 1 read-write SYSRAM1_PARITY_INTREN sysram1_parity_intren 10 1 read-write SYSRAM_STATUS SYSRAM status Register 0x11C 32 read-only n 0x0 0xFFFFFFFF SYSRAM0_PARITY_ERR_ADDR sysram0_parity_err_addr 0 11 read-only SYSRAM1_PARITY_ERR_ADDR sysram1_parity_err_addr 16 11 read-only SYSTICK_CFG SYSTICK confige Register 0x18 32 read-write n 0x0 0xFFFFFFFF NOREF noref 25 1 read-write SKEW skew 24 1 read-write STCALIB stcalib 0 24 read-write TIM1 TIM1 TIMER 0x400AC000 0x0 0x1000 registers n TIM1 TIM1 Interrupt 6 ARR TIMx_ARR register 0x2C 32 read-write n 0x0 0xFFFFFFFF BDTR TIMx_BDTR Register 0x44 32 read-write n 0x0 0xFFFFFFFF AOE Automatic output enable 14 1 read-write BKE Break enable 12 1 read-write BKP Break polarity 13 1 read-write DTG Dead-time generator setup 0 8 read-write MOE Main output enable 15 1 read-write OSSI OSSI 10 1 read-write OSSR OSSR 11 1 read-write CCER Time catch/compare enable Register 0x20 32 read-write n 0x0 0xFFFFFFFF CC1E CC1E 0 1 read-write CC1NE CC1NE 2 1 read-write CC1NP CC1NP 3 1 read-write CC1P CC1P 1 1 read-write CC2E CC2E 4 1 read-write CC2NE CC2NE 6 1 read-write CC2NP CC2NP 7 1 read-write CC2P CC2P 5 1 read-write CC3E CC3E 8 1 read-write CC3NE CC3NE 10 1 read-write CC3NP CC3NP 11 1 read-write CC3P CC3P 9 1 read-write CC4E CC4E 12 1 read-write CC4P CC4P 13 1 read-write CCMR1_CAP Input capture mode TIME Catch/compare mode register CCMR1_COM 0x18 32 read-write n 0x0 0xFFFFFFFF CC1S input capture mode CC1S 0 2 read-write CC2S input capture mode CC2S 8 2 read-write IC1F input capture mode IC1F 4 4 read-write IC1PSC input capture mode IC1PSC 2 2 read-write IC2F input capture mode IC2F 12 4 read-write IC2PSC input capture mode IC2PSC 10 2 read-write CCMR1_COM Output compare mode TIME Catch/compare mode register 0x18 32 read-write n 0x0 0xFFFFFFFF CC1S Output compare mode CC1S 0 2 read-write CC2S Output compare mode CC2S 8 2 read-write OC1CE Output compare mode OC1CE 7 1 read-write OC1FE Output compare mode OC1FE 2 1 read-write OC1M Output compare mode OC1M 4 3 read-write OC1PE Output compare mode OC1PE 3 1 read-write OC2CE Output compare mode OC2CE 15 1 read-write OC2FE Output compare mode OC2FE 10 1 read-write OC2M Output compare mode OC2M 12 3 read-write OC2PE Output compare mode OC2PE 11 1 read-write CCMR2_CAP Input capture mode TIME Catch/compare mode register CCMR2_COM 0x1C 32 read-write n 0x0 0xFFFFFFFF CC3S input capture mode CC3S 0 2 read-write CC4S input capture mode CC4S 8 2 read-write IC3F input capture mode IC3F 4 4 read-write IC3PSC input capture mode IC3PSC 2 2 read-write IC4F input capture mode IC4F 12 4 read-write IC4PSC input capture mode IC4PSC 10 2 read-write CCMR2_COM Output compare mode TIME Catch/compare mode register 0x1C 32 read-write n 0x0 0xFFFFFFFF CC3S Output compare mode CC3S 0 2 read-write CC4S Output compare mode CC4S 8 2 read-write OC3CE Output compare mode OC3CE 7 1 read-write OC3FE Output compare mode OC3FE 2 1 read-write OC3M Output compare mode OC3M 4 3 read-write OC3PE Output compare mode OC3PE 3 1 read-write OC4CE Output compare mode OC4CE 15 1 read-write OC4FE Output compare mode OC4FE 10 1 read-write OC4M Output compare mode OC4M 12 3 read-write OC4PE Output compare mode OC4PE 11 1 read-write CCR1 TIMx_CCR1 register 0x34 32 read-write n 0x0 0xFFFFFFFF CCR2 TIMx_CCR2 register 0x38 32 read-write n 0x0 0xFFFFFFFF CCR3 TIMx_CCR3 register 0x3C 32 read-write n 0x0 0xFFFFFFFF CCR4 TIMx_CCR4 register 0x40 32 read-write n 0x0 0xFFFFFFFF CNT TIMe_CNT register 0x24 32 read-only n 0x0 0xFFFFFFFF CR1 Time Control Register 0x0 32 read-write n 0x0 0xFFFFFFFF ARPE Auto-reload preload enable 7 1 read-write CEN Counter enable 0 1 read-write CKD Clock division 8 2 read-write CMS Center-aligned mode selection 5 2 read-write DIR counter Direction 4 1 read-write OPM One pulse mode 3 1 read-write UDIS Update disable 1 1 read-write URS Update request source 2 1 read-write CR2 Time control2 Register 0x4 32 read-write n 0x0 0xFFFFFFFF CCPC catch/compare preloaded control 0 1 read-write CCUS catch/compare control update selection 2 1 read-write MMS Master mode selection 4 3 read-write OIS1 Output Idle state 1 8 1 read-write OIS1N Output Idle state 1 9 1 read-write OIS2 Output Idle state 2 10 1 read-write OIS2N Output Idle state 2 11 1 read-write OIS3 Output Idle state 3 12 1 read-write OIS3N Output Idle state 3 13 1 read-write OIS4 Output Idle state 4 14 1 read-write TI1S TI1 selection 7 1 read-write DIER Time int enable Register 0xC 32 read-write n 0x0 0xFFFFFFFF BIE BIE 7 1 read-write CC1IE CC1IE 1 1 read-write CC2IE CC2IE 2 1 read-write CC3IE CC3IE 3 1 read-write CC4IE CC4IE 4 1 read-write COMIE COMIE 5 1 read-write TIE TIE 6 1 read-write UIE UIE 0 1 read-write DTG1 TIMX_DTG1 0x48 32 read-write n 0x0 0xFFFFFFFF EGR Time event generate Register 0x14 32 read-write n 0x0 0xFFFFFFFF BG Break generation 7 1 read-write CC1G Capture/Compare 1 generation 1 1 read-write CC2G Capture/Compare 2 generation 2 1 read-write CC3G Capture/Compare 3 generation 3 1 read-write CC4G Capture/Compare 4 generation 4 1 read-write COMG Capture/Compare control update generation 5 1 read-write TG Trigger generation 6 1 read-write UG Update generation 0 1 read-write ISR TIMx_ISR 0x4C 32 read-write n 0x0 0xFFFFFFFF BRK_SEL Brk_sel 10 2 read-write CH1_SEL Ch1_sel 2 2 read-write CH2_SEL Ch2_sel 4 2 read-write CH3_SEL Ch3_sel 6 2 read-write CH4_SEL Ch4_sel 8 2 read-write CNTCAP_CLREN Cnt_cap_clr_en 17 1 read-write CNT_CAP_CLR_SEL Cnt_cap_clr_sel 15 2 read-write DEBUG_MODE Debug_mode 0 2 read-write TRC_SEL Trc_sel 12 3 read-write PSC TIMx_PSC register 0x28 32 read-write n 0x0 0xFFFFFFFF RCR TIMx_RCR register 0x30 32 read-write n 0x0 0xFFFFFFFF SMCR Time slave mode control Register 0x8 32 read-write n 0x0 0xFFFFFFFF ECE External clock enable 14 1 read-write ETF External trigger filter 8 4 read-write ETP External trigger polarity 15 1 read-write ETPS External trigger prescaler 12 2 read-write OCCS Clear OCxREF 3 1 read-write SMS Slave mode selection 0 3 read-write TS Trigger selection 4 3 read-write SR TIME status register 0x10 32 read-write n 0x0 0xFFFFFFFF BIF Break interrupt flag 7 1 read-write CC1IF Capture/Compare 1 interrupt flag 1 1 read-write CC1OF Capture/Compare 1 overcapture flag 9 1 read-write CC2IF Capture/Compare 2 interrupt flag 2 1 read-write CC2OF Capture/Compare 2 overcapture flag 10 1 read-write CC3IF Capture/Compare 3 interrupt flag 3 1 read-write CC3OF Capture/Compare 3 overcapture flag 11 1 read-write CC4IF Capture/Compare 4 interrupt flag 4 1 read-write CC4OF Capture/Compare 4 overcapture flag 12 1 read-write COMIF COM interrupt flag 5 1 read-write TIF Trigger interrupt flag 6 1 read-write UIF Update interrupt flag 0 1 read-write TIM14 TIM1 TIMER 0x400A0000 0x0 0x1000 registers n TIM14 TIM14 Interrupt 23 ARR TIMx_ARR register 0x2C 32 read-write n 0x0 0xFFFFFFFF BDTR TIMx_BDTR Register 0x44 32 read-write n 0x0 0xFFFFFFFF AOE Automatic output enable 14 1 read-write BKE Break enable 12 1 read-write BKP Break polarity 13 1 read-write DTG Dead-time generator setup 0 8 read-write MOE Main output enable 15 1 read-write OSSI OSSI 10 1 read-write OSSR OSSR 11 1 read-write CCER Time catch/compare enable Register 0x20 32 read-write n 0x0 0xFFFFFFFF CC1E CC1E 0 1 read-write CC1NE CC1NE 2 1 read-write CC1NP CC1NP 3 1 read-write CC1P CC1P 1 1 read-write CC2E CC2E 4 1 read-write CC2NE CC2NE 6 1 read-write CC2NP CC2NP 7 1 read-write CC2P CC2P 5 1 read-write CC3E CC3E 8 1 read-write CC3NE CC3NE 10 1 read-write CC3NP CC3NP 11 1 read-write CC3P CC3P 9 1 read-write CC4E CC4E 12 1 read-write CC4P CC4P 13 1 read-write CCMR1_CAP Input capture mode TIME Catch/compare mode register CCMR1_COM 0x18 32 read-write n 0x0 0xFFFFFFFF CC1S input capture mode CC1S 0 2 read-write CC2S input capture mode CC2S 8 2 read-write IC1F input capture mode IC1F 4 4 read-write IC1PSC input capture mode IC1PSC 2 2 read-write IC2F input capture mode IC2F 12 4 read-write IC2PSC input capture mode IC2PSC 10 2 read-write CCMR1_COM Output compare mode TIME Catch/compare mode register 0x18 32 read-write n 0x0 0xFFFFFFFF CC1S Output compare mode CC1S 0 2 read-write CC2S Output compare mode CC2S 8 2 read-write OC1CE Output compare mode OC1CE 7 1 read-write OC1FE Output compare mode OC1FE 2 1 read-write OC1M Output compare mode OC1M 4 3 read-write OC1PE Output compare mode OC1PE 3 1 read-write OC2CE Output compare mode OC2CE 15 1 read-write OC2FE Output compare mode OC2FE 10 1 read-write OC2M Output compare mode OC2M 12 3 read-write OC2PE Output compare mode OC2PE 11 1 read-write CCMR2_CAP Input capture mode TIME Catch/compare mode register CCMR2_COM 0x1C 32 read-write n 0x0 0xFFFFFFFF CC3S input capture mode CC3S 0 2 read-write CC4S input capture mode CC4S 8 2 read-write IC3F input capture mode IC3F 4 4 read-write IC3PSC input capture mode IC3PSC 2 2 read-write IC4F input capture mode IC4F 12 4 read-write IC4PSC input capture mode IC4PSC 10 2 read-write CCMR2_COM Output compare mode TIME Catch/compare mode register 0x1C 32 read-write n 0x0 0xFFFFFFFF CC3S Output compare mode CC3S 0 2 read-write CC4S Output compare mode CC4S 8 2 read-write OC3CE Output compare mode OC3CE 7 1 read-write OC3FE Output compare mode OC3FE 2 1 read-write OC3M Output compare mode OC3M 4 3 read-write OC3PE Output compare mode OC3PE 3 1 read-write OC4CE Output compare mode OC4CE 15 1 read-write OC4FE Output compare mode OC4FE 10 1 read-write OC4M Output compare mode OC4M 12 3 read-write OC4PE Output compare mode OC4PE 11 1 read-write CCR1 TIMx_CCR1 register 0x34 32 read-write n 0x0 0xFFFFFFFF CCR2 TIMx_CCR2 register 0x38 32 read-write n 0x0 0xFFFFFFFF CCR3 TIMx_CCR3 register 0x3C 32 read-write n 0x0 0xFFFFFFFF CCR4 TIMx_CCR4 register 0x40 32 read-write n 0x0 0xFFFFFFFF CNT TIMe_CNT register 0x24 32 read-only n 0x0 0xFFFFFFFF CR1 Time Control Register 0x0 32 read-write n 0x0 0xFFFFFFFF ARPE Auto-reload preload enable 7 1 read-write CEN Counter enable 0 1 read-write CKD Clock division 8 2 read-write CMS Center-aligned mode selection 5 2 read-write DIR counter Direction 4 1 read-write OPM One pulse mode 3 1 read-write UDIS Update disable 1 1 read-write URS Update request source 2 1 read-write CR2 Time control2 Register 0x4 32 read-write n 0x0 0xFFFFFFFF CCPC catch/compare preloaded control 0 1 read-write CCUS catch/compare control update selection 2 1 read-write MMS Master mode selection 4 3 read-write OIS1 Output Idle state 1 8 1 read-write OIS1N Output Idle state 1 9 1 read-write OIS2 Output Idle state 2 10 1 read-write OIS2N Output Idle state 2 11 1 read-write OIS3 Output Idle state 3 12 1 read-write OIS3N Output Idle state 3 13 1 read-write OIS4 Output Idle state 4 14 1 read-write TI1S TI1 selection 7 1 read-write DIER Time int enable Register 0xC 32 read-write n 0x0 0xFFFFFFFF BIE BIE 7 1 read-write CC1IE CC1IE 1 1 read-write CC2IE CC2IE 2 1 read-write CC3IE CC3IE 3 1 read-write CC4IE CC4IE 4 1 read-write COMIE COMIE 5 1 read-write TIE TIE 6 1 read-write UIE UIE 0 1 read-write DTG1 TIMX_DTG1 0x48 32 read-write n 0x0 0xFFFFFFFF EGR Time event generate Register 0x14 32 read-write n 0x0 0xFFFFFFFF BG Break generation 7 1 read-write CC1G Capture/Compare 1 generation 1 1 read-write CC2G Capture/Compare 2 generation 2 1 read-write CC3G Capture/Compare 3 generation 3 1 read-write CC4G Capture/Compare 4 generation 4 1 read-write COMG Capture/Compare control update generation 5 1 read-write TG Trigger generation 6 1 read-write UG Update generation 0 1 read-write ISR TIMx_ISR 0x4C 32 read-write n 0x0 0xFFFFFFFF BRK_SEL Brk_sel 10 2 read-write CH1_SEL Ch1_sel 2 2 read-write CH2_SEL Ch2_sel 4 2 read-write CH3_SEL Ch3_sel 6 2 read-write CH4_SEL Ch4_sel 8 2 read-write CNTCAP_CLREN Cnt_cap_clr_en 17 1 read-write CNT_CAP_CLR_SEL Cnt_cap_clr_sel 15 2 read-write DEBUG_MODE Debug_mode 0 2 read-write TRC_SEL Trc_sel 12 3 read-write PSC TIMx_PSC register 0x28 32 read-write n 0x0 0xFFFFFFFF RCR TIMx_RCR register 0x30 32 read-write n 0x0 0xFFFFFFFF SMCR Time slave mode control Register 0x8 32 read-write n 0x0 0xFFFFFFFF ECE External clock enable 14 1 read-write ETF External trigger filter 8 4 read-write ETP External trigger polarity 15 1 read-write ETPS External trigger prescaler 12 2 read-write OCCS Clear OCxREF 3 1 read-write SMS Slave mode selection 0 3 read-write TS Trigger selection 4 3 read-write SR TIME status register 0x10 32 read-write n 0x0 0xFFFFFFFF BIF Break interrupt flag 7 1 read-write CC1IF Capture/Compare 1 interrupt flag 1 1 read-write CC1OF Capture/Compare 1 overcapture flag 9 1 read-write CC2IF Capture/Compare 2 interrupt flag 2 1 read-write CC2OF Capture/Compare 2 overcapture flag 10 1 read-write CC3IF Capture/Compare 3 interrupt flag 3 1 read-write CC3OF Capture/Compare 3 overcapture flag 11 1 read-write CC4IF Capture/Compare 4 interrupt flag 4 1 read-write CC4OF Capture/Compare 4 overcapture flag 12 1 read-write COMIF COM interrupt flag 5 1 read-write TIF Trigger interrupt flag 6 1 read-write UIF Update interrupt flag 0 1 read-write TIM15 TIM1 TIMER 0x400A1000 0x0 0x1000 registers n TIM15 TIM15 Interrupt 24 ARR TIMx_ARR register 0x2C 32 read-write n 0x0 0xFFFFFFFF BDTR TIMx_BDTR Register 0x44 32 read-write n 0x0 0xFFFFFFFF AOE Automatic output enable 14 1 read-write BKE Break enable 12 1 read-write BKP Break polarity 13 1 read-write DTG Dead-time generator setup 0 8 read-write MOE Main output enable 15 1 read-write OSSI OSSI 10 1 read-write OSSR OSSR 11 1 read-write CCER Time catch/compare enable Register 0x20 32 read-write n 0x0 0xFFFFFFFF CC1E CC1E 0 1 read-write CC1NE CC1NE 2 1 read-write CC1NP CC1NP 3 1 read-write CC1P CC1P 1 1 read-write CC2E CC2E 4 1 read-write CC2NE CC2NE 6 1 read-write CC2NP CC2NP 7 1 read-write CC2P CC2P 5 1 read-write CC3E CC3E 8 1 read-write CC3NE CC3NE 10 1 read-write CC3NP CC3NP 11 1 read-write CC3P CC3P 9 1 read-write CC4E CC4E 12 1 read-write CC4P CC4P 13 1 read-write CCMR1_CAP Input capture mode TIME Catch/compare mode register CCMR1_COM 0x18 32 read-write n 0x0 0xFFFFFFFF CC1S input capture mode CC1S 0 2 read-write CC2S input capture mode CC2S 8 2 read-write IC1F input capture mode IC1F 4 4 read-write IC1PSC input capture mode IC1PSC 2 2 read-write IC2F input capture mode IC2F 12 4 read-write IC2PSC input capture mode IC2PSC 10 2 read-write CCMR1_COM Output compare mode TIME Catch/compare mode register 0x18 32 read-write n 0x0 0xFFFFFFFF CC1S Output compare mode CC1S 0 2 read-write CC2S Output compare mode CC2S 8 2 read-write OC1CE Output compare mode OC1CE 7 1 read-write OC1FE Output compare mode OC1FE 2 1 read-write OC1M Output compare mode OC1M 4 3 read-write OC1PE Output compare mode OC1PE 3 1 read-write OC2CE Output compare mode OC2CE 15 1 read-write OC2FE Output compare mode OC2FE 10 1 read-write OC2M Output compare mode OC2M 12 3 read-write OC2PE Output compare mode OC2PE 11 1 read-write CCMR2_CAP Input capture mode TIME Catch/compare mode register CCMR2_COM 0x1C 32 read-write n 0x0 0xFFFFFFFF CC3S input capture mode CC3S 0 2 read-write CC4S input capture mode CC4S 8 2 read-write IC3F input capture mode IC3F 4 4 read-write IC3PSC input capture mode IC3PSC 2 2 read-write IC4F input capture mode IC4F 12 4 read-write IC4PSC input capture mode IC4PSC 10 2 read-write CCMR2_COM Output compare mode TIME Catch/compare mode register 0x1C 32 read-write n 0x0 0xFFFFFFFF CC3S Output compare mode CC3S 0 2 read-write CC4S Output compare mode CC4S 8 2 read-write OC3CE Output compare mode OC3CE 7 1 read-write OC3FE Output compare mode OC3FE 2 1 read-write OC3M Output compare mode OC3M 4 3 read-write OC3PE Output compare mode OC3PE 3 1 read-write OC4CE Output compare mode OC4CE 15 1 read-write OC4FE Output compare mode OC4FE 10 1 read-write OC4M Output compare mode OC4M 12 3 read-write OC4PE Output compare mode OC4PE 11 1 read-write CCR1 TIMx_CCR1 register 0x34 32 read-write n 0x0 0xFFFFFFFF CCR2 TIMx_CCR2 register 0x38 32 read-write n 0x0 0xFFFFFFFF CCR3 TIMx_CCR3 register 0x3C 32 read-write n 0x0 0xFFFFFFFF CCR4 TIMx_CCR4 register 0x40 32 read-write n 0x0 0xFFFFFFFF CNT TIMe_CNT register 0x24 32 read-only n 0x0 0xFFFFFFFF CR1 Time Control Register 0x0 32 read-write n 0x0 0xFFFFFFFF ARPE Auto-reload preload enable 7 1 read-write CEN Counter enable 0 1 read-write CKD Clock division 8 2 read-write CMS Center-aligned mode selection 5 2 read-write DIR counter Direction 4 1 read-write OPM One pulse mode 3 1 read-write UDIS Update disable 1 1 read-write URS Update request source 2 1 read-write CR2 Time control2 Register 0x4 32 read-write n 0x0 0xFFFFFFFF CCPC catch/compare preloaded control 0 1 read-write CCUS catch/compare control update selection 2 1 read-write MMS Master mode selection 4 3 read-write OIS1 Output Idle state 1 8 1 read-write OIS1N Output Idle state 1 9 1 read-write OIS2 Output Idle state 2 10 1 read-write OIS2N Output Idle state 2 11 1 read-write OIS3 Output Idle state 3 12 1 read-write OIS3N Output Idle state 3 13 1 read-write OIS4 Output Idle state 4 14 1 read-write TI1S TI1 selection 7 1 read-write DIER Time int enable Register 0xC 32 read-write n 0x0 0xFFFFFFFF BIE BIE 7 1 read-write CC1IE CC1IE 1 1 read-write CC2IE CC2IE 2 1 read-write CC3IE CC3IE 3 1 read-write CC4IE CC4IE 4 1 read-write COMIE COMIE 5 1 read-write TIE TIE 6 1 read-write UIE UIE 0 1 read-write DTG1 TIMX_DTG1 0x48 32 read-write n 0x0 0xFFFFFFFF EGR Time event generate Register 0x14 32 read-write n 0x0 0xFFFFFFFF BG Break generation 7 1 read-write CC1G Capture/Compare 1 generation 1 1 read-write CC2G Capture/Compare 2 generation 2 1 read-write CC3G Capture/Compare 3 generation 3 1 read-write CC4G Capture/Compare 4 generation 4 1 read-write COMG Capture/Compare control update generation 5 1 read-write TG Trigger generation 6 1 read-write UG Update generation 0 1 read-write ISR TIMx_ISR 0x4C 32 read-write n 0x0 0xFFFFFFFF BRK_SEL Brk_sel 10 2 read-write CH1_SEL Ch1_sel 2 2 read-write CH2_SEL Ch2_sel 4 2 read-write CH3_SEL Ch3_sel 6 2 read-write CH4_SEL Ch4_sel 8 2 read-write CNTCAP_CLREN Cnt_cap_clr_en 17 1 read-write CNT_CAP_CLR_SEL Cnt_cap_clr_sel 15 2 read-write DEBUG_MODE Debug_mode 0 2 read-write TRC_SEL Trc_sel 12 3 read-write PSC TIMx_PSC register 0x28 32 read-write n 0x0 0xFFFFFFFF RCR TIMx_RCR register 0x30 32 read-write n 0x0 0xFFFFFFFF SMCR Time slave mode control Register 0x8 32 read-write n 0x0 0xFFFFFFFF ECE External clock enable 14 1 read-write ETF External trigger filter 8 4 read-write ETP External trigger polarity 15 1 read-write ETPS External trigger prescaler 12 2 read-write OCCS Clear OCxREF 3 1 read-write SMS Slave mode selection 0 3 read-write TS Trigger selection 4 3 read-write SR TIME status register 0x10 32 read-write n 0x0 0xFFFFFFFF BIF Break interrupt flag 7 1 read-write CC1IF Capture/Compare 1 interrupt flag 1 1 read-write CC1OF Capture/Compare 1 overcapture flag 9 1 read-write CC2IF Capture/Compare 2 interrupt flag 2 1 read-write CC2OF Capture/Compare 2 overcapture flag 10 1 read-write CC3IF Capture/Compare 3 interrupt flag 3 1 read-write CC3OF Capture/Compare 3 overcapture flag 11 1 read-write CC4IF Capture/Compare 4 interrupt flag 4 1 read-write CC4OF Capture/Compare 4 overcapture flag 12 1 read-write COMIF COM interrupt flag 5 1 read-write TIF Trigger interrupt flag 6 1 read-write UIF Update interrupt flag 0 1 read-write TIM16 TIM1 TIMER 0x400A2000 0x0 0x1000 registers n TIM16 TIM16 Interrupt 25 ARR TIMx_ARR register 0x2C 32 read-write n 0x0 0xFFFFFFFF BDTR TIMx_BDTR Register 0x44 32 read-write n 0x0 0xFFFFFFFF AOE Automatic output enable 14 1 read-write BKE Break enable 12 1 read-write BKP Break polarity 13 1 read-write DTG Dead-time generator setup 0 8 read-write MOE Main output enable 15 1 read-write OSSI OSSI 10 1 read-write OSSR OSSR 11 1 read-write CCER Time catch/compare enable Register 0x20 32 read-write n 0x0 0xFFFFFFFF CC1E CC1E 0 1 read-write CC1NE CC1NE 2 1 read-write CC1NP CC1NP 3 1 read-write CC1P CC1P 1 1 read-write CC2E CC2E 4 1 read-write CC2NE CC2NE 6 1 read-write CC2NP CC2NP 7 1 read-write CC2P CC2P 5 1 read-write CC3E CC3E 8 1 read-write CC3NE CC3NE 10 1 read-write CC3NP CC3NP 11 1 read-write CC3P CC3P 9 1 read-write CC4E CC4E 12 1 read-write CC4P CC4P 13 1 read-write CCMR1_CAP Input capture mode TIME Catch/compare mode register CCMR1_COM 0x18 32 read-write n 0x0 0xFFFFFFFF CC1S input capture mode CC1S 0 2 read-write CC2S input capture mode CC2S 8 2 read-write IC1F input capture mode IC1F 4 4 read-write IC1PSC input capture mode IC1PSC 2 2 read-write IC2F input capture mode IC2F 12 4 read-write IC2PSC input capture mode IC2PSC 10 2 read-write CCMR1_COM Output compare mode TIME Catch/compare mode register 0x18 32 read-write n 0x0 0xFFFFFFFF CC1S Output compare mode CC1S 0 2 read-write CC2S Output compare mode CC2S 8 2 read-write OC1CE Output compare mode OC1CE 7 1 read-write OC1FE Output compare mode OC1FE 2 1 read-write OC1M Output compare mode OC1M 4 3 read-write OC1PE Output compare mode OC1PE 3 1 read-write OC2CE Output compare mode OC2CE 15 1 read-write OC2FE Output compare mode OC2FE 10 1 read-write OC2M Output compare mode OC2M 12 3 read-write OC2PE Output compare mode OC2PE 11 1 read-write CCMR2_CAP Input capture mode TIME Catch/compare mode register CCMR2_COM 0x1C 32 read-write n 0x0 0xFFFFFFFF CC3S input capture mode CC3S 0 2 read-write CC4S input capture mode CC4S 8 2 read-write IC3F input capture mode IC3F 4 4 read-write IC3PSC input capture mode IC3PSC 2 2 read-write IC4F input capture mode IC4F 12 4 read-write IC4PSC input capture mode IC4PSC 10 2 read-write CCMR2_COM Output compare mode TIME Catch/compare mode register 0x1C 32 read-write n 0x0 0xFFFFFFFF CC3S Output compare mode CC3S 0 2 read-write CC4S Output compare mode CC4S 8 2 read-write OC3CE Output compare mode OC3CE 7 1 read-write OC3FE Output compare mode OC3FE 2 1 read-write OC3M Output compare mode OC3M 4 3 read-write OC3PE Output compare mode OC3PE 3 1 read-write OC4CE Output compare mode OC4CE 15 1 read-write OC4FE Output compare mode OC4FE 10 1 read-write OC4M Output compare mode OC4M 12 3 read-write OC4PE Output compare mode OC4PE 11 1 read-write CCR1 TIMx_CCR1 register 0x34 32 read-write n 0x0 0xFFFFFFFF CCR2 TIMx_CCR2 register 0x38 32 read-write n 0x0 0xFFFFFFFF CCR3 TIMx_CCR3 register 0x3C 32 read-write n 0x0 0xFFFFFFFF CCR4 TIMx_CCR4 register 0x40 32 read-write n 0x0 0xFFFFFFFF CNT TIMe_CNT register 0x24 32 read-only n 0x0 0xFFFFFFFF CR1 Time Control Register 0x0 32 read-write n 0x0 0xFFFFFFFF ARPE Auto-reload preload enable 7 1 read-write CEN Counter enable 0 1 read-write CKD Clock division 8 2 read-write CMS Center-aligned mode selection 5 2 read-write DIR counter Direction 4 1 read-write OPM One pulse mode 3 1 read-write UDIS Update disable 1 1 read-write URS Update request source 2 1 read-write CR2 Time control2 Register 0x4 32 read-write n 0x0 0xFFFFFFFF CCPC catch/compare preloaded control 0 1 read-write CCUS catch/compare control update selection 2 1 read-write MMS Master mode selection 4 3 read-write OIS1 Output Idle state 1 8 1 read-write OIS1N Output Idle state 1 9 1 read-write OIS2 Output Idle state 2 10 1 read-write OIS2N Output Idle state 2 11 1 read-write OIS3 Output Idle state 3 12 1 read-write OIS3N Output Idle state 3 13 1 read-write OIS4 Output Idle state 4 14 1 read-write TI1S TI1 selection 7 1 read-write DIER Time int enable Register 0xC 32 read-write n 0x0 0xFFFFFFFF BIE BIE 7 1 read-write CC1IE CC1IE 1 1 read-write CC2IE CC2IE 2 1 read-write CC3IE CC3IE 3 1 read-write CC4IE CC4IE 4 1 read-write COMIE COMIE 5 1 read-write TIE TIE 6 1 read-write UIE UIE 0 1 read-write DTG1 TIMX_DTG1 0x48 32 read-write n 0x0 0xFFFFFFFF EGR Time event generate Register 0x14 32 read-write n 0x0 0xFFFFFFFF BG Break generation 7 1 read-write CC1G Capture/Compare 1 generation 1 1 read-write CC2G Capture/Compare 2 generation 2 1 read-write CC3G Capture/Compare 3 generation 3 1 read-write CC4G Capture/Compare 4 generation 4 1 read-write COMG Capture/Compare control update generation 5 1 read-write TG Trigger generation 6 1 read-write UG Update generation 0 1 read-write ISR TIMx_ISR 0x4C 32 read-write n 0x0 0xFFFFFFFF BRK_SEL Brk_sel 10 2 read-write CH1_SEL Ch1_sel 2 2 read-write CH2_SEL Ch2_sel 4 2 read-write CH3_SEL Ch3_sel 6 2 read-write CH4_SEL Ch4_sel 8 2 read-write CNTCAP_CLREN Cnt_cap_clr_en 17 1 read-write CNT_CAP_CLR_SEL Cnt_cap_clr_sel 15 2 read-write DEBUG_MODE Debug_mode 0 2 read-write TRC_SEL Trc_sel 12 3 read-write PSC TIMx_PSC register 0x28 32 read-write n 0x0 0xFFFFFFFF RCR TIMx_RCR register 0x30 32 read-write n 0x0 0xFFFFFFFF SMCR Time slave mode control Register 0x8 32 read-write n 0x0 0xFFFFFFFF ECE External clock enable 14 1 read-write ETF External trigger filter 8 4 read-write ETP External trigger polarity 15 1 read-write ETPS External trigger prescaler 12 2 read-write OCCS Clear OCxREF 3 1 read-write SMS Slave mode selection 0 3 read-write TS Trigger selection 4 3 read-write SR TIME status register 0x10 32 read-write n 0x0 0xFFFFFFFF BIF Break interrupt flag 7 1 read-write CC1IF Capture/Compare 1 interrupt flag 1 1 read-write CC1OF Capture/Compare 1 overcapture flag 9 1 read-write CC2IF Capture/Compare 2 interrupt flag 2 1 read-write CC2OF Capture/Compare 2 overcapture flag 10 1 read-write CC3IF Capture/Compare 3 interrupt flag 3 1 read-write CC3OF Capture/Compare 3 overcapture flag 11 1 read-write CC4IF Capture/Compare 4 interrupt flag 4 1 read-write CC4OF Capture/Compare 4 overcapture flag 12 1 read-write COMIF COM interrupt flag 5 1 read-write TIF Trigger interrupt flag 6 1 read-write UIF Update interrupt flag 0 1 read-write TIM17 TIM1 TIMER 0x400A3000 0x0 0x1000 registers n TIM17 TIM17 Interrupt 26 ARR TIMx_ARR register 0x2C 32 read-write n 0x0 0xFFFFFFFF BDTR TIMx_BDTR Register 0x44 32 read-write n 0x0 0xFFFFFFFF AOE Automatic output enable 14 1 read-write BKE Break enable 12 1 read-write BKP Break polarity 13 1 read-write DTG Dead-time generator setup 0 8 read-write MOE Main output enable 15 1 read-write OSSI OSSI 10 1 read-write OSSR OSSR 11 1 read-write CCER Time catch/compare enable Register 0x20 32 read-write n 0x0 0xFFFFFFFF CC1E CC1E 0 1 read-write CC1NE CC1NE 2 1 read-write CC1NP CC1NP 3 1 read-write CC1P CC1P 1 1 read-write CC2E CC2E 4 1 read-write CC2NE CC2NE 6 1 read-write CC2NP CC2NP 7 1 read-write CC2P CC2P 5 1 read-write CC3E CC3E 8 1 read-write CC3NE CC3NE 10 1 read-write CC3NP CC3NP 11 1 read-write CC3P CC3P 9 1 read-write CC4E CC4E 12 1 read-write CC4P CC4P 13 1 read-write CCMR1_CAP Input capture mode TIME Catch/compare mode register CCMR1_COM 0x18 32 read-write n 0x0 0xFFFFFFFF CC1S input capture mode CC1S 0 2 read-write CC2S input capture mode CC2S 8 2 read-write IC1F input capture mode IC1F 4 4 read-write IC1PSC input capture mode IC1PSC 2 2 read-write IC2F input capture mode IC2F 12 4 read-write IC2PSC input capture mode IC2PSC 10 2 read-write CCMR1_COM Output compare mode TIME Catch/compare mode register 0x18 32 read-write n 0x0 0xFFFFFFFF CC1S Output compare mode CC1S 0 2 read-write CC2S Output compare mode CC2S 8 2 read-write OC1CE Output compare mode OC1CE 7 1 read-write OC1FE Output compare mode OC1FE 2 1 read-write OC1M Output compare mode OC1M 4 3 read-write OC1PE Output compare mode OC1PE 3 1 read-write OC2CE Output compare mode OC2CE 15 1 read-write OC2FE Output compare mode OC2FE 10 1 read-write OC2M Output compare mode OC2M 12 3 read-write OC2PE Output compare mode OC2PE 11 1 read-write CCMR2_CAP Input capture mode TIME Catch/compare mode register CCMR2_COM 0x1C 32 read-write n 0x0 0xFFFFFFFF CC3S input capture mode CC3S 0 2 read-write CC4S input capture mode CC4S 8 2 read-write IC3F input capture mode IC3F 4 4 read-write IC3PSC input capture mode IC3PSC 2 2 read-write IC4F input capture mode IC4F 12 4 read-write IC4PSC input capture mode IC4PSC 10 2 read-write CCMR2_COM Output compare mode TIME Catch/compare mode register 0x1C 32 read-write n 0x0 0xFFFFFFFF CC3S Output compare mode CC3S 0 2 read-write CC4S Output compare mode CC4S 8 2 read-write OC3CE Output compare mode OC3CE 7 1 read-write OC3FE Output compare mode OC3FE 2 1 read-write OC3M Output compare mode OC3M 4 3 read-write OC3PE Output compare mode OC3PE 3 1 read-write OC4CE Output compare mode OC4CE 15 1 read-write OC4FE Output compare mode OC4FE 10 1 read-write OC4M Output compare mode OC4M 12 3 read-write OC4PE Output compare mode OC4PE 11 1 read-write CCR1 TIMx_CCR1 register 0x34 32 read-write n 0x0 0xFFFFFFFF CCR2 TIMx_CCR2 register 0x38 32 read-write n 0x0 0xFFFFFFFF CCR3 TIMx_CCR3 register 0x3C 32 read-write n 0x0 0xFFFFFFFF CCR4 TIMx_CCR4 register 0x40 32 read-write n 0x0 0xFFFFFFFF CNT TIMe_CNT register 0x24 32 read-only n 0x0 0xFFFFFFFF CR1 Time Control Register 0x0 32 read-write n 0x0 0xFFFFFFFF ARPE Auto-reload preload enable 7 1 read-write CEN Counter enable 0 1 read-write CKD Clock division 8 2 read-write CMS Center-aligned mode selection 5 2 read-write DIR counter Direction 4 1 read-write OPM One pulse mode 3 1 read-write UDIS Update disable 1 1 read-write URS Update request source 2 1 read-write CR2 Time control2 Register 0x4 32 read-write n 0x0 0xFFFFFFFF CCPC catch/compare preloaded control 0 1 read-write CCUS catch/compare control update selection 2 1 read-write MMS Master mode selection 4 3 read-write OIS1 Output Idle state 1 8 1 read-write OIS1N Output Idle state 1 9 1 read-write OIS2 Output Idle state 2 10 1 read-write OIS2N Output Idle state 2 11 1 read-write OIS3 Output Idle state 3 12 1 read-write OIS3N Output Idle state 3 13 1 read-write OIS4 Output Idle state 4 14 1 read-write TI1S TI1 selection 7 1 read-write DIER Time int enable Register 0xC 32 read-write n 0x0 0xFFFFFFFF BIE BIE 7 1 read-write CC1IE CC1IE 1 1 read-write CC2IE CC2IE 2 1 read-write CC3IE CC3IE 3 1 read-write CC4IE CC4IE 4 1 read-write COMIE COMIE 5 1 read-write TIE TIE 6 1 read-write UIE UIE 0 1 read-write DTG1 TIMX_DTG1 0x48 32 read-write n 0x0 0xFFFFFFFF EGR Time event generate Register 0x14 32 read-write n 0x0 0xFFFFFFFF BG Break generation 7 1 read-write CC1G Capture/Compare 1 generation 1 1 read-write CC2G Capture/Compare 2 generation 2 1 read-write CC3G Capture/Compare 3 generation 3 1 read-write CC4G Capture/Compare 4 generation 4 1 read-write COMG Capture/Compare control update generation 5 1 read-write TG Trigger generation 6 1 read-write UG Update generation 0 1 read-write ISR TIMx_ISR 0x4C 32 read-write n 0x0 0xFFFFFFFF BRK_SEL Brk_sel 10 2 read-write CH1_SEL Ch1_sel 2 2 read-write CH2_SEL Ch2_sel 4 2 read-write CH3_SEL Ch3_sel 6 2 read-write CH4_SEL Ch4_sel 8 2 read-write CNTCAP_CLREN Cnt_cap_clr_en 17 1 read-write CNT_CAP_CLR_SEL Cnt_cap_clr_sel 15 2 read-write DEBUG_MODE Debug_mode 0 2 read-write TRC_SEL Trc_sel 12 3 read-write PSC TIMx_PSC register 0x28 32 read-write n 0x0 0xFFFFFFFF RCR TIMx_RCR register 0x30 32 read-write n 0x0 0xFFFFFFFF SMCR Time slave mode control Register 0x8 32 read-write n 0x0 0xFFFFFFFF ECE External clock enable 14 1 read-write ETF External trigger filter 8 4 read-write ETP External trigger polarity 15 1 read-write ETPS External trigger prescaler 12 2 read-write OCCS Clear OCxREF 3 1 read-write SMS Slave mode selection 0 3 read-write TS Trigger selection 4 3 read-write SR TIME status register 0x10 32 read-write n 0x0 0xFFFFFFFF BIF Break interrupt flag 7 1 read-write CC1IF Capture/Compare 1 interrupt flag 1 1 read-write CC1OF Capture/Compare 1 overcapture flag 9 1 read-write CC2IF Capture/Compare 2 interrupt flag 2 1 read-write CC2OF Capture/Compare 2 overcapture flag 10 1 read-write CC3IF Capture/Compare 3 interrupt flag 3 1 read-write CC3OF Capture/Compare 3 overcapture flag 11 1 read-write CC4IF Capture/Compare 4 interrupt flag 4 1 read-write CC4OF Capture/Compare 4 overcapture flag 12 1 read-write COMIF COM interrupt flag 5 1 read-write TIF Trigger interrupt flag 6 1 read-write UIF Update interrupt flag 0 1 read-write TIM3 TIM1 TIMER 0x400AD000 0x0 0x1000 registers n TIM3 TIM3 Interrupt 7 ARR TIMx_ARR register 0x2C 32 read-write n 0x0 0xFFFFFFFF BDTR TIMx_BDTR Register 0x44 32 read-write n 0x0 0xFFFFFFFF AOE Automatic output enable 14 1 read-write BKE Break enable 12 1 read-write BKP Break polarity 13 1 read-write DTG Dead-time generator setup 0 8 read-write MOE Main output enable 15 1 read-write OSSI OSSI 10 1 read-write OSSR OSSR 11 1 read-write CCER Time catch/compare enable Register 0x20 32 read-write n 0x0 0xFFFFFFFF CC1E CC1E 0 1 read-write CC1NE CC1NE 2 1 read-write CC1NP CC1NP 3 1 read-write CC1P CC1P 1 1 read-write CC2E CC2E 4 1 read-write CC2NE CC2NE 6 1 read-write CC2NP CC2NP 7 1 read-write CC2P CC2P 5 1 read-write CC3E CC3E 8 1 read-write CC3NE CC3NE 10 1 read-write CC3NP CC3NP 11 1 read-write CC3P CC3P 9 1 read-write CC4E CC4E 12 1 read-write CC4P CC4P 13 1 read-write CCMR1_CAP Input capture mode TIME Catch/compare mode register CCMR1_COM 0x18 32 read-write n 0x0 0xFFFFFFFF CC1S input capture mode CC1S 0 2 read-write CC2S input capture mode CC2S 8 2 read-write IC1F input capture mode IC1F 4 4 read-write IC1PSC input capture mode IC1PSC 2 2 read-write IC2F input capture mode IC2F 12 4 read-write IC2PSC input capture mode IC2PSC 10 2 read-write CCMR1_COM Output compare mode TIME Catch/compare mode register 0x18 32 read-write n 0x0 0xFFFFFFFF CC1S Output compare mode CC1S 0 2 read-write CC2S Output compare mode CC2S 8 2 read-write OC1CE Output compare mode OC1CE 7 1 read-write OC1FE Output compare mode OC1FE 2 1 read-write OC1M Output compare mode OC1M 4 3 read-write OC1PE Output compare mode OC1PE 3 1 read-write OC2CE Output compare mode OC2CE 15 1 read-write OC2FE Output compare mode OC2FE 10 1 read-write OC2M Output compare mode OC2M 12 3 read-write OC2PE Output compare mode OC2PE 11 1 read-write CCMR2_CAP Input capture mode TIME Catch/compare mode register CCMR2_COM 0x1C 32 read-write n 0x0 0xFFFFFFFF CC3S input capture mode CC3S 0 2 read-write CC4S input capture mode CC4S 8 2 read-write IC3F input capture mode IC3F 4 4 read-write IC3PSC input capture mode IC3PSC 2 2 read-write IC4F input capture mode IC4F 12 4 read-write IC4PSC input capture mode IC4PSC 10 2 read-write CCMR2_COM Output compare mode TIME Catch/compare mode register 0x1C 32 read-write n 0x0 0xFFFFFFFF CC3S Output compare mode CC3S 0 2 read-write CC4S Output compare mode CC4S 8 2 read-write OC3CE Output compare mode OC3CE 7 1 read-write OC3FE Output compare mode OC3FE 2 1 read-write OC3M Output compare mode OC3M 4 3 read-write OC3PE Output compare mode OC3PE 3 1 read-write OC4CE Output compare mode OC4CE 15 1 read-write OC4FE Output compare mode OC4FE 10 1 read-write OC4M Output compare mode OC4M 12 3 read-write OC4PE Output compare mode OC4PE 11 1 read-write CCR1 TIMx_CCR1 register 0x34 32 read-write n 0x0 0xFFFFFFFF CCR2 TIMx_CCR2 register 0x38 32 read-write n 0x0 0xFFFFFFFF CCR3 TIMx_CCR3 register 0x3C 32 read-write n 0x0 0xFFFFFFFF CCR4 TIMx_CCR4 register 0x40 32 read-write n 0x0 0xFFFFFFFF CNT TIMe_CNT register 0x24 32 read-only n 0x0 0xFFFFFFFF CR1 Time Control Register 0x0 32 read-write n 0x0 0xFFFFFFFF ARPE Auto-reload preload enable 7 1 read-write CEN Counter enable 0 1 read-write CKD Clock division 8 2 read-write CMS Center-aligned mode selection 5 2 read-write DIR counter Direction 4 1 read-write OPM One pulse mode 3 1 read-write UDIS Update disable 1 1 read-write URS Update request source 2 1 read-write CR2 Time control2 Register 0x4 32 read-write n 0x0 0xFFFFFFFF CCPC catch/compare preloaded control 0 1 read-write CCUS catch/compare control update selection 2 1 read-write MMS Master mode selection 4 3 read-write OIS1 Output Idle state 1 8 1 read-write OIS1N Output Idle state 1 9 1 read-write OIS2 Output Idle state 2 10 1 read-write OIS2N Output Idle state 2 11 1 read-write OIS3 Output Idle state 3 12 1 read-write OIS3N Output Idle state 3 13 1 read-write OIS4 Output Idle state 4 14 1 read-write TI1S TI1 selection 7 1 read-write DIER Time int enable Register 0xC 32 read-write n 0x0 0xFFFFFFFF BIE BIE 7 1 read-write CC1IE CC1IE 1 1 read-write CC2IE CC2IE 2 1 read-write CC3IE CC3IE 3 1 read-write CC4IE CC4IE 4 1 read-write COMIE COMIE 5 1 read-write TIE TIE 6 1 read-write UIE UIE 0 1 read-write DTG1 TIMX_DTG1 0x48 32 read-write n 0x0 0xFFFFFFFF EGR Time event generate Register 0x14 32 read-write n 0x0 0xFFFFFFFF BG Break generation 7 1 read-write CC1G Capture/Compare 1 generation 1 1 read-write CC2G Capture/Compare 2 generation 2 1 read-write CC3G Capture/Compare 3 generation 3 1 read-write CC4G Capture/Compare 4 generation 4 1 read-write COMG Capture/Compare control update generation 5 1 read-write TG Trigger generation 6 1 read-write UG Update generation 0 1 read-write ISR TIMx_ISR 0x4C 32 read-write n 0x0 0xFFFFFFFF BRK_SEL Brk_sel 10 2 read-write CH1_SEL Ch1_sel 2 2 read-write CH2_SEL Ch2_sel 4 2 read-write CH3_SEL Ch3_sel 6 2 read-write CH4_SEL Ch4_sel 8 2 read-write CNTCAP_CLREN Cnt_cap_clr_en 17 1 read-write CNT_CAP_CLR_SEL Cnt_cap_clr_sel 15 2 read-write DEBUG_MODE Debug_mode 0 2 read-write TRC_SEL Trc_sel 12 3 read-write PSC TIMx_PSC register 0x28 32 read-write n 0x0 0xFFFFFFFF RCR TIMx_RCR register 0x30 32 read-write n 0x0 0xFFFFFFFF SMCR Time slave mode control Register 0x8 32 read-write n 0x0 0xFFFFFFFF ECE External clock enable 14 1 read-write ETF External trigger filter 8 4 read-write ETP External trigger polarity 15 1 read-write ETPS External trigger prescaler 12 2 read-write OCCS Clear OCxREF 3 1 read-write SMS Slave mode selection 0 3 read-write TS Trigger selection 4 3 read-write SR TIME status register 0x10 32 read-write n 0x0 0xFFFFFFFF BIF Break interrupt flag 7 1 read-write CC1IF Capture/Compare 1 interrupt flag 1 1 read-write CC1OF Capture/Compare 1 overcapture flag 9 1 read-write CC2IF Capture/Compare 2 interrupt flag 2 1 read-write CC2OF Capture/Compare 2 overcapture flag 10 1 read-write CC3IF Capture/Compare 3 interrupt flag 3 1 read-write CC3OF Capture/Compare 3 overcapture flag 11 1 read-write CC4IF Capture/Compare 4 interrupt flag 4 1 read-write CC4OF Capture/Compare 4 overcapture flag 12 1 read-write COMIF COM interrupt flag 5 1 read-write TIF Trigger interrupt flag 6 1 read-write UIF Update interrupt flag 0 1 read-write UART1 UART1 UART 0x40090000 0x0 0x4C registers n UART1 UART1 Interrupt 0 UARTCR UART0 Control Register 0x30 32 read-write n 0x0 0xFFFFFFFF CTSEN Clear to Send hardware flow control enable 15 1 read-write DTR Data Transmit Ready 10 1 read-write LBE Loopback Enable 7 1 read-write OUT1 Out1 12 1 read-write OUT2 Out2 13 1 read-write RTS Request to Send 11 1 read-write RTSEN Ready to Send hardware flow control enable 14 1 read-write RXE Receive Enable 9 1 read-write SIREN SIR ENDEC Enable 1 1 read-write SIRLP SIR low-power IrDA mode 2 1 read-write TXE Transmit Enable 8 1 read-write UARTEN UART Enable 0 1 read-write UARTDMACR UART0 DMA Control Register 0x48 32 read-write n 0x0 0xFFFFFFFF DMA_ERROR nUARTDCD Modem Interrupt mask 2 1 read-write RXFIFO_EN nUARTRI Modem Interrupt mask 0 1 read-write TXFIFO_EN nUARTCTS Modem Interrupt mask 1 1 read-write UARTDR uart data buff 0x0 32 read-write n 0x0 0xFFFFFFFF BREAK_ERROR DMA Transmit Size 10 1 read-write DATA UART0 Send And Recive Data 0 8 read-write FRAMING_ERROR DMA Transmit Size 8 1 read-write OVERRUN_ERROR DMA Transmit Size 11 1 read-write PARITY_ERROR DMA Transmit Size 9 1 read-write UARTFBRD uart board rate mod 0..5 is usefull 0x28 32 read-write n 0x0 0xFFFFFFFF UARTFR UART0 Flag Register 0x18 32 read-only n 0x0 0xFFFFFFFF BUSY Indicate Is Busy 3 1 read-only CTS Clear to Send 0 1 read-only RXFE Receive FIFO Empty 4 1 read-only RXFF Receive FIFO Full 6 1 read-only TXFE Transmit FIFO Empty 7 1 read-only TXFF Transmit FIFO Full 5 1 read-only UARTIBRD uart board rate 0..15 is usefull 0x24 32 read-write n 0x0 0xFFFFFFFF UARTICR UART0 Int Clear Register 0x44 32 write-only n 0x0 0xFFFFFFFF C_BE_IM Clear Break Error Interrupt Mask 9 1 write-only C_FE_IM Clear Framing Error Interrupt Mask 7 1 write-only C_NUARTCTS_IM Clear nUARTCTS Modem Interrupt mask 1 1 write-only C_NUARTDCD_IM Clear nUARTDCD Modem Interrupt mask 2 1 write-only C_NUARTDSR_IM Clear nUARTDSR Modem Interrupt mask 3 1 write-only C_NUARTRI_IM Clear nUARTRI Modem Interrupt mask 0 1 write-only C_OE_IM Clear Overrun Error Interrupt Mask 10 1 write-only C_PF_IM Clear Parity Error Interrupt Mask 8 1 write-only C_RECEIVE_IM Clear Receive Interrupt Mask 4 1 write-only C_RT_IM Clear Receive Ttimeout Interrupt Mask 6 1 write-only C_TRANSMIT_IM Clear Transmit Interrupt Mask 5 1 write-only UARTIFLS fifo int level select 0x34 32 read-write n 0x12 0xFFFFFFFF RXIFLSEL Receive Interrupt FIFO Level Select 3 3 read-write TXIFLSEL Transmit Interrupt FIFO Level Select 0 3 read-write UARTIMSC int enable bit 0x38 32 read-write n 0x0 0xFFFFFFFF BEIM Break Error Interrupt Mask 9 1 read-write CTSMIM nUARTCTS Modem Interrupt mask 1 1 read-write DCDMIM nUARTDCD Modem Interrupt mask 2 1 read-write DSRMIM nUARTDSR Modem Interrupt mask 3 1 read-write FEIM Framing Error Interrupt Mask 7 1 read-write OEIM Overrun Error Interrupt Mask 10 1 read-write PEIM Parity Error Interrupt Mask 8 1 read-write RIMIM nUARTRI Modem Interrupt mask 0 1 read-write RTIM Receive Ttimeout Interrupt Mask 6 1 read-write RXIM Receive Interrupt Mask 4 1 read-write TXIM Transmit Interrupt Mask 5 1 read-write UARTLCR_H Line Control 0x2C 32 read-write n 0x0 0xFFFFFFFF BRK Send Break 0 1 read-write EPS Even Parity Select 2 1 read-write FEN FIFO Enable 4 1 read-write PEN Parity Enable 1 1 read-write SPS Stick Parity Select 7 1 read-write STP2 2 Stop Bits 3 1 read-write WLEN Word Length 5 2 read-write UARTMIS UART0 MASK Interrupt 0x40 32 read-only n 0x0 0xFFFFFFFF BE_MI Break Error Masked Interrupt 9 1 read-only FE_MI Framing Error Masked Interrupt 7 1 read-only NUARTCTS_MI nUARTCTS Modem Masked Interrupt 1 1 read-only NUARTDCD_MI nUARTDCD Modem Masked Interrupt 2 1 read-only NUARTDSR_MI nUARTDSR Modem Masked Interrupt 3 1 read-only NUARTRI_MI nUARTRI Modem Masked Interrupt 0 1 read-only OE_MI Overrun Error Masked Interrupt 10 1 read-only PF_MI Parity Error Masked Interrupt 8 1 read-only RECEIVE_MI Receive Masked Interrupt 4 1 read-only RT_MI Receive Ttimeout Masked Interrupt 6 1 read-only TRANSMIT_MI Transmit Masked Interrupt 5 1 read-only UARTRIS UART0 Int Rigio 0x3C 32 read-only n 0x0 0xFFFFFFFF BE_I Break Error Interrupt 9 1 read-only FE_I Framing Error Interrupt 7 1 read-only NUARTCTS_I nUARTCTS Modem Interrupt 1 1 read-only NUARTDCD_I nUARTDCD Modem Interrupt 2 1 read-only NUARTDSR_I nUARTDSR Modem Interrupt 3 1 read-only NUARTRI_I nUARTRI Modem Interrupt 0 1 read-only OE_I Overrun Error Interrupt 10 1 read-only PF_I Parity Error Interrupt 8 1 read-only RECEIVE_I Receive Interrupt 4 1 read-only RT_I Receive Ttimeout Interrupt 6 1 read-only TRANSMIT_I Transmit Interrupt 5 1 read-only UARTRSR uart rx status 0x4 32 read-write n 0x0 0xFFFFFFFF BREAK_ERROR DMA Transmit Size 2 1 read-write FRAMING_ERROR DMA Transmit Size 0 1 read-write OVERRUN_ERROR DMA Transmit Size 3 1 read-write PARITY_ERROR DMA Transmit Size 1 1 read-write UART2 UART1 UART 0x40091000 0x0 0x4C registers n UART2 Uart2 Interrupt 1 UARTCR UART0 Control Register 0x30 32 read-write n 0x0 0xFFFFFFFF CTSEN Clear to Send hardware flow control enable 15 1 read-write DTR Data Transmit Ready 10 1 read-write LBE Loopback Enable 7 1 read-write OUT1 Out1 12 1 read-write OUT2 Out2 13 1 read-write RTS Request to Send 11 1 read-write RTSEN Ready to Send hardware flow control enable 14 1 read-write RXE Receive Enable 9 1 read-write SIREN SIR ENDEC Enable 1 1 read-write SIRLP SIR low-power IrDA mode 2 1 read-write TXE Transmit Enable 8 1 read-write UARTEN UART Enable 0 1 read-write UARTDMACR UART0 DMA Control Register 0x48 32 read-write n 0x0 0xFFFFFFFF DMA_ERROR nUARTDCD Modem Interrupt mask 2 1 read-write RXFIFO_EN nUARTRI Modem Interrupt mask 0 1 read-write TXFIFO_EN nUARTCTS Modem Interrupt mask 1 1 read-write UARTDR uart data buff 0x0 32 read-write n 0x0 0xFFFFFFFF BREAK_ERROR DMA Transmit Size 10 1 read-write DATA UART0 Send And Recive Data 0 8 read-write FRAMING_ERROR DMA Transmit Size 8 1 read-write OVERRUN_ERROR DMA Transmit Size 11 1 read-write PARITY_ERROR DMA Transmit Size 9 1 read-write UARTFBRD uart board rate mod 0..5 is usefull 0x28 32 read-write n 0x0 0xFFFFFFFF UARTFR UART0 Flag Register 0x18 32 read-only n 0x0 0xFFFFFFFF BUSY Indicate Is Busy 3 1 read-only CTS Clear to Send 0 1 read-only RXFE Receive FIFO Empty 4 1 read-only RXFF Receive FIFO Full 6 1 read-only TXFE Transmit FIFO Empty 7 1 read-only TXFF Transmit FIFO Full 5 1 read-only UARTIBRD uart board rate 0..15 is usefull 0x24 32 read-write n 0x0 0xFFFFFFFF UARTICR UART0 Int Clear Register 0x44 32 write-only n 0x0 0xFFFFFFFF C_BE_IM Clear Break Error Interrupt Mask 9 1 write-only C_FE_IM Clear Framing Error Interrupt Mask 7 1 write-only C_NUARTCTS_IM Clear nUARTCTS Modem Interrupt mask 1 1 write-only C_NUARTDCD_IM Clear nUARTDCD Modem Interrupt mask 2 1 write-only C_NUARTDSR_IM Clear nUARTDSR Modem Interrupt mask 3 1 write-only C_NUARTRI_IM Clear nUARTRI Modem Interrupt mask 0 1 write-only C_OE_IM Clear Overrun Error Interrupt Mask 10 1 write-only C_PF_IM Clear Parity Error Interrupt Mask 8 1 write-only C_RECEIVE_IM Clear Receive Interrupt Mask 4 1 write-only C_RT_IM Clear Receive Ttimeout Interrupt Mask 6 1 write-only C_TRANSMIT_IM Clear Transmit Interrupt Mask 5 1 write-only UARTIFLS fifo int level select 0x34 32 read-write n 0x12 0xFFFFFFFF RXIFLSEL Receive Interrupt FIFO Level Select 3 3 read-write TXIFLSEL Transmit Interrupt FIFO Level Select 0 3 read-write UARTIMSC int enable bit 0x38 32 read-write n 0x0 0xFFFFFFFF BEIM Break Error Interrupt Mask 9 1 read-write CTSMIM nUARTCTS Modem Interrupt mask 1 1 read-write DCDMIM nUARTDCD Modem Interrupt mask 2 1 read-write DSRMIM nUARTDSR Modem Interrupt mask 3 1 read-write FEIM Framing Error Interrupt Mask 7 1 read-write OEIM Overrun Error Interrupt Mask 10 1 read-write PEIM Parity Error Interrupt Mask 8 1 read-write RIMIM nUARTRI Modem Interrupt mask 0 1 read-write RTIM Receive Ttimeout Interrupt Mask 6 1 read-write RXIM Receive Interrupt Mask 4 1 read-write TXIM Transmit Interrupt Mask 5 1 read-write UARTLCR_H Line Control 0x2C 32 read-write n 0x0 0xFFFFFFFF BRK Send Break 0 1 read-write EPS Even Parity Select 2 1 read-write FEN FIFO Enable 4 1 read-write PEN Parity Enable 1 1 read-write SPS Stick Parity Select 7 1 read-write STP2 2 Stop Bits 3 1 read-write WLEN Word Length 5 2 read-write UARTMIS UART0 MASK Interrupt 0x40 32 read-only n 0x0 0xFFFFFFFF BE_MI Break Error Masked Interrupt 9 1 read-only FE_MI Framing Error Masked Interrupt 7 1 read-only NUARTCTS_MI nUARTCTS Modem Masked Interrupt 1 1 read-only NUARTDCD_MI nUARTDCD Modem Masked Interrupt 2 1 read-only NUARTDSR_MI nUARTDSR Modem Masked Interrupt 3 1 read-only NUARTRI_MI nUARTRI Modem Masked Interrupt 0 1 read-only OE_MI Overrun Error Masked Interrupt 10 1 read-only PF_MI Parity Error Masked Interrupt 8 1 read-only RECEIVE_MI Receive Masked Interrupt 4 1 read-only RT_MI Receive Ttimeout Masked Interrupt 6 1 read-only TRANSMIT_MI Transmit Masked Interrupt 5 1 read-only UARTRIS UART0 Int Rigio 0x3C 32 read-only n 0x0 0xFFFFFFFF BE_I Break Error Interrupt 9 1 read-only FE_I Framing Error Interrupt 7 1 read-only NUARTCTS_I nUARTCTS Modem Interrupt 1 1 read-only NUARTDCD_I nUARTDCD Modem Interrupt 2 1 read-only NUARTDSR_I nUARTDSR Modem Interrupt 3 1 read-only NUARTRI_I nUARTRI Modem Interrupt 0 1 read-only OE_I Overrun Error Interrupt 10 1 read-only PF_I Parity Error Interrupt 8 1 read-only RECEIVE_I Receive Interrupt 4 1 read-only RT_I Receive Ttimeout Interrupt 6 1 read-only TRANSMIT_I Transmit Interrupt 5 1 read-only UARTRSR uart rx status 0x4 32 read-write n 0x0 0xFFFFFFFF BREAK_ERROR DMA Transmit Size 2 1 read-write FRAMING_ERROR DMA Transmit Size 0 1 read-write OVERRUN_ERROR DMA Transmit Size 3 1 read-write PARITY_ERROR DMA Transmit Size 1 1 read-write UART3 UART1 UART 0x40092000 0x0 0x4C registers n UART3 Uart3 Interrupt 2 UARTCR UART0 Control Register 0x30 32 read-write n 0x0 0xFFFFFFFF CTSEN Clear to Send hardware flow control enable 15 1 read-write DTR Data Transmit Ready 10 1 read-write LBE Loopback Enable 7 1 read-write OUT1 Out1 12 1 read-write OUT2 Out2 13 1 read-write RTS Request to Send 11 1 read-write RTSEN Ready to Send hardware flow control enable 14 1 read-write RXE Receive Enable 9 1 read-write SIREN SIR ENDEC Enable 1 1 read-write SIRLP SIR low-power IrDA mode 2 1 read-write TXE Transmit Enable 8 1 read-write UARTEN UART Enable 0 1 read-write UARTDMACR UART0 DMA Control Register 0x48 32 read-write n 0x0 0xFFFFFFFF DMA_ERROR nUARTDCD Modem Interrupt mask 2 1 read-write RXFIFO_EN nUARTRI Modem Interrupt mask 0 1 read-write TXFIFO_EN nUARTCTS Modem Interrupt mask 1 1 read-write UARTDR uart data buff 0x0 32 read-write n 0x0 0xFFFFFFFF BREAK_ERROR DMA Transmit Size 10 1 read-write DATA UART0 Send And Recive Data 0 8 read-write FRAMING_ERROR DMA Transmit Size 8 1 read-write OVERRUN_ERROR DMA Transmit Size 11 1 read-write PARITY_ERROR DMA Transmit Size 9 1 read-write UARTFBRD uart board rate mod 0..5 is usefull 0x28 32 read-write n 0x0 0xFFFFFFFF UARTFR UART0 Flag Register 0x18 32 read-only n 0x0 0xFFFFFFFF BUSY Indicate Is Busy 3 1 read-only CTS Clear to Send 0 1 read-only RXFE Receive FIFO Empty 4 1 read-only RXFF Receive FIFO Full 6 1 read-only TXFE Transmit FIFO Empty 7 1 read-only TXFF Transmit FIFO Full 5 1 read-only UARTIBRD uart board rate 0..15 is usefull 0x24 32 read-write n 0x0 0xFFFFFFFF UARTICR UART0 Int Clear Register 0x44 32 write-only n 0x0 0xFFFFFFFF C_BE_IM Clear Break Error Interrupt Mask 9 1 write-only C_FE_IM Clear Framing Error Interrupt Mask 7 1 write-only C_NUARTCTS_IM Clear nUARTCTS Modem Interrupt mask 1 1 write-only C_NUARTDCD_IM Clear nUARTDCD Modem Interrupt mask 2 1 write-only C_NUARTDSR_IM Clear nUARTDSR Modem Interrupt mask 3 1 write-only C_NUARTRI_IM Clear nUARTRI Modem Interrupt mask 0 1 write-only C_OE_IM Clear Overrun Error Interrupt Mask 10 1 write-only C_PF_IM Clear Parity Error Interrupt Mask 8 1 write-only C_RECEIVE_IM Clear Receive Interrupt Mask 4 1 write-only C_RT_IM Clear Receive Ttimeout Interrupt Mask 6 1 write-only C_TRANSMIT_IM Clear Transmit Interrupt Mask 5 1 write-only UARTIFLS fifo int level select 0x34 32 read-write n 0x12 0xFFFFFFFF RXIFLSEL Receive Interrupt FIFO Level Select 3 3 read-write TXIFLSEL Transmit Interrupt FIFO Level Select 0 3 read-write UARTIMSC int enable bit 0x38 32 read-write n 0x0 0xFFFFFFFF BEIM Break Error Interrupt Mask 9 1 read-write CTSMIM nUARTCTS Modem Interrupt mask 1 1 read-write DCDMIM nUARTDCD Modem Interrupt mask 2 1 read-write DSRMIM nUARTDSR Modem Interrupt mask 3 1 read-write FEIM Framing Error Interrupt Mask 7 1 read-write OEIM Overrun Error Interrupt Mask 10 1 read-write PEIM Parity Error Interrupt Mask 8 1 read-write RIMIM nUARTRI Modem Interrupt mask 0 1 read-write RTIM Receive Ttimeout Interrupt Mask 6 1 read-write RXIM Receive Interrupt Mask 4 1 read-write TXIM Transmit Interrupt Mask 5 1 read-write UARTLCR_H Line Control 0x2C 32 read-write n 0x0 0xFFFFFFFF BRK Send Break 0 1 read-write EPS Even Parity Select 2 1 read-write FEN FIFO Enable 4 1 read-write PEN Parity Enable 1 1 read-write SPS Stick Parity Select 7 1 read-write STP2 2 Stop Bits 3 1 read-write WLEN Word Length 5 2 read-write UARTMIS UART0 MASK Interrupt 0x40 32 read-only n 0x0 0xFFFFFFFF BE_MI Break Error Masked Interrupt 9 1 read-only FE_MI Framing Error Masked Interrupt 7 1 read-only NUARTCTS_MI nUARTCTS Modem Masked Interrupt 1 1 read-only NUARTDCD_MI nUARTDCD Modem Masked Interrupt 2 1 read-only NUARTDSR_MI nUARTDSR Modem Masked Interrupt 3 1 read-only NUARTRI_MI nUARTRI Modem Masked Interrupt 0 1 read-only OE_MI Overrun Error Masked Interrupt 10 1 read-only PF_MI Parity Error Masked Interrupt 8 1 read-only RECEIVE_MI Receive Masked Interrupt 4 1 read-only RT_MI Receive Ttimeout Masked Interrupt 6 1 read-only TRANSMIT_MI Transmit Masked Interrupt 5 1 read-only UARTRIS UART0 Int Rigio 0x3C 32 read-only n 0x0 0xFFFFFFFF BE_I Break Error Interrupt 9 1 read-only FE_I Framing Error Interrupt 7 1 read-only NUARTCTS_I nUARTCTS Modem Interrupt 1 1 read-only NUARTDCD_I nUARTDCD Modem Interrupt 2 1 read-only NUARTDSR_I nUARTDSR Modem Interrupt 3 1 read-only NUARTRI_I nUARTRI Modem Interrupt 0 1 read-only OE_I Overrun Error Interrupt 10 1 read-only PF_I Parity Error Interrupt 8 1 read-only RECEIVE_I Receive Interrupt 4 1 read-only RT_I Receive Ttimeout Interrupt 6 1 read-only TRANSMIT_I Transmit Interrupt 5 1 read-only UARTRSR uart rx status 0x4 32 read-write n 0x0 0xFFFFFFFF BREAK_ERROR DMA Transmit Size 2 1 read-write FRAMING_ERROR DMA Transmit Size 0 1 read-write OVERRUN_ERROR DMA Transmit Size 3 1 read-write PARITY_ERROR DMA Transmit Size 1 1 read-write UART4 UART1 UART 0x40093000 0x0 0x4C registers n UART4 Uart4 Interrupt 8 UARTCR UART0 Control Register 0x30 32 read-write n 0x0 0xFFFFFFFF CTSEN Clear to Send hardware flow control enable 15 1 read-write DTR Data Transmit Ready 10 1 read-write LBE Loopback Enable 7 1 read-write OUT1 Out1 12 1 read-write OUT2 Out2 13 1 read-write RTS Request to Send 11 1 read-write RTSEN Ready to Send hardware flow control enable 14 1 read-write RXE Receive Enable 9 1 read-write SIREN SIR ENDEC Enable 1 1 read-write SIRLP SIR low-power IrDA mode 2 1 read-write TXE Transmit Enable 8 1 read-write UARTEN UART Enable 0 1 read-write UARTDMACR UART0 DMA Control Register 0x48 32 read-write n 0x0 0xFFFFFFFF DMA_ERROR nUARTDCD Modem Interrupt mask 2 1 read-write RXFIFO_EN nUARTRI Modem Interrupt mask 0 1 read-write TXFIFO_EN nUARTCTS Modem Interrupt mask 1 1 read-write UARTDR uart data buff 0x0 32 read-write n 0x0 0xFFFFFFFF BREAK_ERROR DMA Transmit Size 10 1 read-write DATA UART0 Send And Recive Data 0 8 read-write FRAMING_ERROR DMA Transmit Size 8 1 read-write OVERRUN_ERROR DMA Transmit Size 11 1 read-write PARITY_ERROR DMA Transmit Size 9 1 read-write UARTFBRD uart board rate mod 0..5 is usefull 0x28 32 read-write n 0x0 0xFFFFFFFF UARTFR UART0 Flag Register 0x18 32 read-only n 0x0 0xFFFFFFFF BUSY Indicate Is Busy 3 1 read-only CTS Clear to Send 0 1 read-only RXFE Receive FIFO Empty 4 1 read-only RXFF Receive FIFO Full 6 1 read-only TXFE Transmit FIFO Empty 7 1 read-only TXFF Transmit FIFO Full 5 1 read-only UARTIBRD uart board rate 0..15 is usefull 0x24 32 read-write n 0x0 0xFFFFFFFF UARTICR UART0 Int Clear Register 0x44 32 write-only n 0x0 0xFFFFFFFF C_BE_IM Clear Break Error Interrupt Mask 9 1 write-only C_FE_IM Clear Framing Error Interrupt Mask 7 1 write-only C_NUARTCTS_IM Clear nUARTCTS Modem Interrupt mask 1 1 write-only C_NUARTDCD_IM Clear nUARTDCD Modem Interrupt mask 2 1 write-only C_NUARTDSR_IM Clear nUARTDSR Modem Interrupt mask 3 1 write-only C_NUARTRI_IM Clear nUARTRI Modem Interrupt mask 0 1 write-only C_OE_IM Clear Overrun Error Interrupt Mask 10 1 write-only C_PF_IM Clear Parity Error Interrupt Mask 8 1 write-only C_RECEIVE_IM Clear Receive Interrupt Mask 4 1 write-only C_RT_IM Clear Receive Ttimeout Interrupt Mask 6 1 write-only C_TRANSMIT_IM Clear Transmit Interrupt Mask 5 1 write-only UARTIFLS fifo int level select 0x34 32 read-write n 0x12 0xFFFFFFFF RXIFLSEL Receive Interrupt FIFO Level Select 3 3 read-write TXIFLSEL Transmit Interrupt FIFO Level Select 0 3 read-write UARTIMSC int enable bit 0x38 32 read-write n 0x0 0xFFFFFFFF BEIM Break Error Interrupt Mask 9 1 read-write CTSMIM nUARTCTS Modem Interrupt mask 1 1 read-write DCDMIM nUARTDCD Modem Interrupt mask 2 1 read-write DSRMIM nUARTDSR Modem Interrupt mask 3 1 read-write FEIM Framing Error Interrupt Mask 7 1 read-write OEIM Overrun Error Interrupt Mask 10 1 read-write PEIM Parity Error Interrupt Mask 8 1 read-write RIMIM nUARTRI Modem Interrupt mask 0 1 read-write RTIM Receive Ttimeout Interrupt Mask 6 1 read-write RXIM Receive Interrupt Mask 4 1 read-write TXIM Transmit Interrupt Mask 5 1 read-write UARTLCR_H Line Control 0x2C 32 read-write n 0x0 0xFFFFFFFF BRK Send Break 0 1 read-write EPS Even Parity Select 2 1 read-write FEN FIFO Enable 4 1 read-write PEN Parity Enable 1 1 read-write SPS Stick Parity Select 7 1 read-write STP2 2 Stop Bits 3 1 read-write WLEN Word Length 5 2 read-write UARTMIS UART0 MASK Interrupt 0x40 32 read-only n 0x0 0xFFFFFFFF BE_MI Break Error Masked Interrupt 9 1 read-only FE_MI Framing Error Masked Interrupt 7 1 read-only NUARTCTS_MI nUARTCTS Modem Masked Interrupt 1 1 read-only NUARTDCD_MI nUARTDCD Modem Masked Interrupt 2 1 read-only NUARTDSR_MI nUARTDSR Modem Masked Interrupt 3 1 read-only NUARTRI_MI nUARTRI Modem Masked Interrupt 0 1 read-only OE_MI Overrun Error Masked Interrupt 10 1 read-only PF_MI Parity Error Masked Interrupt 8 1 read-only RECEIVE_MI Receive Masked Interrupt 4 1 read-only RT_MI Receive Ttimeout Masked Interrupt 6 1 read-only TRANSMIT_MI Transmit Masked Interrupt 5 1 read-only UARTRIS UART0 Int Rigio 0x3C 32 read-only n 0x0 0xFFFFFFFF BE_I Break Error Interrupt 9 1 read-only FE_I Framing Error Interrupt 7 1 read-only NUARTCTS_I nUARTCTS Modem Interrupt 1 1 read-only NUARTDCD_I nUARTDCD Modem Interrupt 2 1 read-only NUARTDSR_I nUARTDSR Modem Interrupt 3 1 read-only NUARTRI_I nUARTRI Modem Interrupt 0 1 read-only OE_I Overrun Error Interrupt 10 1 read-only PF_I Parity Error Interrupt 8 1 read-only RECEIVE_I Receive Interrupt 4 1 read-only RT_I Receive Ttimeout Interrupt 6 1 read-only TRANSMIT_I Transmit Interrupt 5 1 read-only UARTRSR uart rx status 0x4 32 read-write n 0x0 0xFFFFFFFF BREAK_ERROR DMA Transmit Size 2 1 read-write FRAMING_ERROR DMA Transmit Size 0 1 read-write OVERRUN_ERROR DMA Transmit Size 3 1 read-write PARITY_ERROR DMA Transmit Size 1 1 read-write UART5 UART1 UART 0x40094000 0x0 0x4C registers n UART5 Uart5 Interrupt 9 UARTCR UART0 Control Register 0x30 32 read-write n 0x0 0xFFFFFFFF CTSEN Clear to Send hardware flow control enable 15 1 read-write DTR Data Transmit Ready 10 1 read-write LBE Loopback Enable 7 1 read-write OUT1 Out1 12 1 read-write OUT2 Out2 13 1 read-write RTS Request to Send 11 1 read-write RTSEN Ready to Send hardware flow control enable 14 1 read-write RXE Receive Enable 9 1 read-write SIREN SIR ENDEC Enable 1 1 read-write SIRLP SIR low-power IrDA mode 2 1 read-write TXE Transmit Enable 8 1 read-write UARTEN UART Enable 0 1 read-write UARTDMACR UART0 DMA Control Register 0x48 32 read-write n 0x0 0xFFFFFFFF DMA_ERROR nUARTDCD Modem Interrupt mask 2 1 read-write RXFIFO_EN nUARTRI Modem Interrupt mask 0 1 read-write TXFIFO_EN nUARTCTS Modem Interrupt mask 1 1 read-write UARTDR uart data buff 0x0 32 read-write n 0x0 0xFFFFFFFF BREAK_ERROR DMA Transmit Size 10 1 read-write DATA UART0 Send And Recive Data 0 8 read-write FRAMING_ERROR DMA Transmit Size 8 1 read-write OVERRUN_ERROR DMA Transmit Size 11 1 read-write PARITY_ERROR DMA Transmit Size 9 1 read-write UARTFBRD uart board rate mod 0..5 is usefull 0x28 32 read-write n 0x0 0xFFFFFFFF UARTFR UART0 Flag Register 0x18 32 read-only n 0x0 0xFFFFFFFF BUSY Indicate Is Busy 3 1 read-only CTS Clear to Send 0 1 read-only RXFE Receive FIFO Empty 4 1 read-only RXFF Receive FIFO Full 6 1 read-only TXFE Transmit FIFO Empty 7 1 read-only TXFF Transmit FIFO Full 5 1 read-only UARTIBRD uart board rate 0..15 is usefull 0x24 32 read-write n 0x0 0xFFFFFFFF UARTICR UART0 Int Clear Register 0x44 32 write-only n 0x0 0xFFFFFFFF C_BE_IM Clear Break Error Interrupt Mask 9 1 write-only C_FE_IM Clear Framing Error Interrupt Mask 7 1 write-only C_NUARTCTS_IM Clear nUARTCTS Modem Interrupt mask 1 1 write-only C_NUARTDCD_IM Clear nUARTDCD Modem Interrupt mask 2 1 write-only C_NUARTDSR_IM Clear nUARTDSR Modem Interrupt mask 3 1 write-only C_NUARTRI_IM Clear nUARTRI Modem Interrupt mask 0 1 write-only C_OE_IM Clear Overrun Error Interrupt Mask 10 1 write-only C_PF_IM Clear Parity Error Interrupt Mask 8 1 write-only C_RECEIVE_IM Clear Receive Interrupt Mask 4 1 write-only C_RT_IM Clear Receive Ttimeout Interrupt Mask 6 1 write-only C_TRANSMIT_IM Clear Transmit Interrupt Mask 5 1 write-only UARTIFLS fifo int level select 0x34 32 read-write n 0x12 0xFFFFFFFF RXIFLSEL Receive Interrupt FIFO Level Select 3 3 read-write TXIFLSEL Transmit Interrupt FIFO Level Select 0 3 read-write UARTIMSC int enable bit 0x38 32 read-write n 0x0 0xFFFFFFFF BEIM Break Error Interrupt Mask 9 1 read-write CTSMIM nUARTCTS Modem Interrupt mask 1 1 read-write DCDMIM nUARTDCD Modem Interrupt mask 2 1 read-write DSRMIM nUARTDSR Modem Interrupt mask 3 1 read-write FEIM Framing Error Interrupt Mask 7 1 read-write OEIM Overrun Error Interrupt Mask 10 1 read-write PEIM Parity Error Interrupt Mask 8 1 read-write RIMIM nUARTRI Modem Interrupt mask 0 1 read-write RTIM Receive Ttimeout Interrupt Mask 6 1 read-write RXIM Receive Interrupt Mask 4 1 read-write TXIM Transmit Interrupt Mask 5 1 read-write UARTLCR_H Line Control 0x2C 32 read-write n 0x0 0xFFFFFFFF BRK Send Break 0 1 read-write EPS Even Parity Select 2 1 read-write FEN FIFO Enable 4 1 read-write PEN Parity Enable 1 1 read-write SPS Stick Parity Select 7 1 read-write STP2 2 Stop Bits 3 1 read-write WLEN Word Length 5 2 read-write UARTMIS UART0 MASK Interrupt 0x40 32 read-only n 0x0 0xFFFFFFFF BE_MI Break Error Masked Interrupt 9 1 read-only FE_MI Framing Error Masked Interrupt 7 1 read-only NUARTCTS_MI nUARTCTS Modem Masked Interrupt 1 1 read-only NUARTDCD_MI nUARTDCD Modem Masked Interrupt 2 1 read-only NUARTDSR_MI nUARTDSR Modem Masked Interrupt 3 1 read-only NUARTRI_MI nUARTRI Modem Masked Interrupt 0 1 read-only OE_MI Overrun Error Masked Interrupt 10 1 read-only PF_MI Parity Error Masked Interrupt 8 1 read-only RECEIVE_MI Receive Masked Interrupt 4 1 read-only RT_MI Receive Ttimeout Masked Interrupt 6 1 read-only TRANSMIT_MI Transmit Masked Interrupt 5 1 read-only UARTRIS UART0 Int Rigio 0x3C 32 read-only n 0x0 0xFFFFFFFF BE_I Break Error Interrupt 9 1 read-only FE_I Framing Error Interrupt 7 1 read-only NUARTCTS_I nUARTCTS Modem Interrupt 1 1 read-only NUARTDCD_I nUARTDCD Modem Interrupt 2 1 read-only NUARTDSR_I nUARTDSR Modem Interrupt 3 1 read-only NUARTRI_I nUARTRI Modem Interrupt 0 1 read-only OE_I Overrun Error Interrupt 10 1 read-only PF_I Parity Error Interrupt 8 1 read-only RECEIVE_I Receive Interrupt 4 1 read-only RT_I Receive Ttimeout Interrupt 6 1 read-only TRANSMIT_I Transmit Interrupt 5 1 read-only UARTRSR uart rx status 0x4 32 read-write n 0x0 0xFFFFFFFF BREAK_ERROR DMA Transmit Size 2 1 read-write FRAMING_ERROR DMA Transmit Size 0 1 read-write OVERRUN_ERROR DMA Transmit Size 3 1 read-write PARITY_ERROR DMA Transmit Size 1 1 read-write UART6 UART1 UART 0x40095000 0x0 0x4C registers n UART6 Uart6 Interrupt 10 UARTCR UART0 Control Register 0x30 32 read-write n 0x0 0xFFFFFFFF CTSEN Clear to Send hardware flow control enable 15 1 read-write DTR Data Transmit Ready 10 1 read-write LBE Loopback Enable 7 1 read-write OUT1 Out1 12 1 read-write OUT2 Out2 13 1 read-write RTS Request to Send 11 1 read-write RTSEN Ready to Send hardware flow control enable 14 1 read-write RXE Receive Enable 9 1 read-write SIREN SIR ENDEC Enable 1 1 read-write SIRLP SIR low-power IrDA mode 2 1 read-write TXE Transmit Enable 8 1 read-write UARTEN UART Enable 0 1 read-write UARTDMACR UART0 DMA Control Register 0x48 32 read-write n 0x0 0xFFFFFFFF DMA_ERROR nUARTDCD Modem Interrupt mask 2 1 read-write RXFIFO_EN nUARTRI Modem Interrupt mask 0 1 read-write TXFIFO_EN nUARTCTS Modem Interrupt mask 1 1 read-write UARTDR uart data buff 0x0 32 read-write n 0x0 0xFFFFFFFF BREAK_ERROR DMA Transmit Size 10 1 read-write DATA UART0 Send And Recive Data 0 8 read-write FRAMING_ERROR DMA Transmit Size 8 1 read-write OVERRUN_ERROR DMA Transmit Size 11 1 read-write PARITY_ERROR DMA Transmit Size 9 1 read-write UARTFBRD uart board rate mod 0..5 is usefull 0x28 32 read-write n 0x0 0xFFFFFFFF UARTFR UART0 Flag Register 0x18 32 read-only n 0x0 0xFFFFFFFF BUSY Indicate Is Busy 3 1 read-only CTS Clear to Send 0 1 read-only RXFE Receive FIFO Empty 4 1 read-only RXFF Receive FIFO Full 6 1 read-only TXFE Transmit FIFO Empty 7 1 read-only TXFF Transmit FIFO Full 5 1 read-only UARTIBRD uart board rate 0..15 is usefull 0x24 32 read-write n 0x0 0xFFFFFFFF UARTICR UART0 Int Clear Register 0x44 32 write-only n 0x0 0xFFFFFFFF C_BE_IM Clear Break Error Interrupt Mask 9 1 write-only C_FE_IM Clear Framing Error Interrupt Mask 7 1 write-only C_NUARTCTS_IM Clear nUARTCTS Modem Interrupt mask 1 1 write-only C_NUARTDCD_IM Clear nUARTDCD Modem Interrupt mask 2 1 write-only C_NUARTDSR_IM Clear nUARTDSR Modem Interrupt mask 3 1 write-only C_NUARTRI_IM Clear nUARTRI Modem Interrupt mask 0 1 write-only C_OE_IM Clear Overrun Error Interrupt Mask 10 1 write-only C_PF_IM Clear Parity Error Interrupt Mask 8 1 write-only C_RECEIVE_IM Clear Receive Interrupt Mask 4 1 write-only C_RT_IM Clear Receive Ttimeout Interrupt Mask 6 1 write-only C_TRANSMIT_IM Clear Transmit Interrupt Mask 5 1 write-only UARTIFLS fifo int level select 0x34 32 read-write n 0x12 0xFFFFFFFF RXIFLSEL Receive Interrupt FIFO Level Select 3 3 read-write TXIFLSEL Transmit Interrupt FIFO Level Select 0 3 read-write UARTIMSC int enable bit 0x38 32 read-write n 0x0 0xFFFFFFFF BEIM Break Error Interrupt Mask 9 1 read-write CTSMIM nUARTCTS Modem Interrupt mask 1 1 read-write DCDMIM nUARTDCD Modem Interrupt mask 2 1 read-write DSRMIM nUARTDSR Modem Interrupt mask 3 1 read-write FEIM Framing Error Interrupt Mask 7 1 read-write OEIM Overrun Error Interrupt Mask 10 1 read-write PEIM Parity Error Interrupt Mask 8 1 read-write RIMIM nUARTRI Modem Interrupt mask 0 1 read-write RTIM Receive Ttimeout Interrupt Mask 6 1 read-write RXIM Receive Interrupt Mask 4 1 read-write TXIM Transmit Interrupt Mask 5 1 read-write UARTLCR_H Line Control 0x2C 32 read-write n 0x0 0xFFFFFFFF BRK Send Break 0 1 read-write EPS Even Parity Select 2 1 read-write FEN FIFO Enable 4 1 read-write PEN Parity Enable 1 1 read-write SPS Stick Parity Select 7 1 read-write STP2 2 Stop Bits 3 1 read-write WLEN Word Length 5 2 read-write UARTMIS UART0 MASK Interrupt 0x40 32 read-only n 0x0 0xFFFFFFFF BE_MI Break Error Masked Interrupt 9 1 read-only FE_MI Framing Error Masked Interrupt 7 1 read-only NUARTCTS_MI nUARTCTS Modem Masked Interrupt 1 1 read-only NUARTDCD_MI nUARTDCD Modem Masked Interrupt 2 1 read-only NUARTDSR_MI nUARTDSR Modem Masked Interrupt 3 1 read-only NUARTRI_MI nUARTRI Modem Masked Interrupt 0 1 read-only OE_MI Overrun Error Masked Interrupt 10 1 read-only PF_MI Parity Error Masked Interrupt 8 1 read-only RECEIVE_MI Receive Masked Interrupt 4 1 read-only RT_MI Receive Ttimeout Masked Interrupt 6 1 read-only TRANSMIT_MI Transmit Masked Interrupt 5 1 read-only UARTRIS UART0 Int Rigio 0x3C 32 read-only n 0x0 0xFFFFFFFF BE_I Break Error Interrupt 9 1 read-only FE_I Framing Error Interrupt 7 1 read-only NUARTCTS_I nUARTCTS Modem Interrupt 1 1 read-only NUARTDCD_I nUARTDCD Modem Interrupt 2 1 read-only NUARTDSR_I nUARTDSR Modem Interrupt 3 1 read-only NUARTRI_I nUARTRI Modem Interrupt 0 1 read-only OE_I Overrun Error Interrupt 10 1 read-only PF_I Parity Error Interrupt 8 1 read-only RECEIVE_I Receive Interrupt 4 1 read-only RT_I Receive Ttimeout Interrupt 6 1 read-only TRANSMIT_I Transmit Interrupt 5 1 read-only UARTRSR uart rx status 0x4 32 read-write n 0x0 0xFFFFFFFF BREAK_ERROR DMA Transmit Size 2 1 read-write FRAMING_ERROR DMA Transmit Size 0 1 read-write OVERRUN_ERROR DMA Transmit Size 3 1 read-write PARITY_ERROR DMA Transmit Size 1 1 read-write WDT WDT WDT 0x4008C000 0x0 0xC04 registers n WWDT WWDT Interrupt 14 WDOGCONTROL WDT Control Register 0x8 32 read-write n 0x0 0xFFFFFFFF INTEN Interrput Enable Control Bit 0 1 read-write RSTEN RST Enable Control Bit 1 1 read-write WDOGINTCLR WDT Interrput Clear 0xC 32 write-only n 0x0 0xFFFFFFFF WDOGLOAD WDT Reload Register 0x0 32 read-write n 0xFFFFFFFF 0xFFFFFFFF WDOGLOCK WDT Locked Register 0xC00 32 read-write n 0x0 0xFFFFFFFF WDOGMIS WDT Mask Interrput 0x14 32 read-only n 0x0 0xFFFFFFFF WDOGMINT WDT Mask Interrput flag Bit 0 1 read-only WDOGRIS WDT Original Interrput 0x10 32 read-only n 0x0 0xFFFFFFFF WDOGINT WDT Original Interrput flag Bit 0 1 read-only WDOGVALUE WDT Current Counter 0x4 32 read-only n 0xFFFFFFFF 0xFFFFFFFF