silan SPC7L64A 2024.12.10 SPC7L64A M0 CM0 r0p0 little 2 false 8 32 ACMP ACMP ACMP 0x400AA000 0x0 0x80 registers n ACMP_OPA ACMP_OPA Interrupt 5 CP0CFG CP0CFG Register 0x4 32 read-write n 0xFFFF 0xFFFFFFFF C0CLKD C0CLKD 12 5 read-write C0DFILT C0DFILT 20 10 read-write C0FLG C0FLG 11 1 read-write C0GCEN C0GCEN 3 1 read-write C0GCS C0GCS 4 4 read-write C0INTM C0INTM 8 1 read-write C0INTS C0INTS 9 2 read-write C0OINV C0OINV 0 1 read-write CP0CON CP0CON Register 0x0 32 read-write n 0x0 0xFFFFFFFF C0AFILT C0AFILT 22 1 read-write C0EN C0EN 20 1 read-write C0HYSEN C0HYSEN 8 1 read-write C0NS C0NS 4 2 read-write C0OPS C0OPS 0 2 read-write C0PS C0PS 21 1 read-write C0RDS C0RDS 15 5 read-write C0REFEN C0REFEN 11 1 read-write C0VRHS C0VRHS 12 1 read-write C0VRRH C0VRRH 13 1 read-write C0VRRL C0VRRL 14 1 read-write CP10CFG CP10CFG Register 0x14 32 read-write n 0xFFFF 0xFFFFFFFF C10CLKD C10CLKD 12 5 read-write C10DFILT C10DFILT 20 10 read-write C10FLG C10FLG 11 1 read-write C10GCEN C10GCEN 3 1 read-write C10GCS C10GCS 4 4 read-write C10INTM C10INTM 8 1 read-write C10INTS C10INTS 9 2 read-write C10OINV C10OINV 0 1 read-write CP1CON CP1CON Register 0x10 32 read-write n 0xFFFF 0xFFFFFFFF C10AFILT C10AFILT 22 1 read-write C10EN C10EN 20 1 read-write C10PS C10PS 21 1 read-write C1HYSEN C1HYSEN 8 1 read-write C1HYSS C1HYSS 9 2 read-write C1NS C1NS 4 3 read-write C1OPS C1OPS 0 2 read-write C1RDS C1RDS 15 4 read-write C1REFEN C1REFEN 11 1 read-write C1VRHS C1VRHS 12 1 read-write C1VRRH C1VRRH 13 1 read-write C1VRRL C1VRRL 14 1 read-write OP0CON OP0_CFG Register 0x40 32 read-write n 0x0 0xFFFFFFFF OP0EN OP0EN 0 1 read-write OP0GS OP0GS 16 3 read-write OP0NGD OP0NGD 5 1 read-write OP0NS OP0NS 2 1 read-write OP0OE OP0OE 12 1 read-write OP0OTS OP0OTS 6 1 read-write OP0TM OP0TM 3 1 read-write OP0TM1 OP0TM1 31 1 read-write OP1CON OP1_CFG Register 0x44 32 read-write n 0x0 0xFFFFFFFF OP1EN OP1EN 0 1 read-write OP1GS OP1GS 16 3 read-write OP1NRS OP1NRS 9 1 read-write OP1NS OP1NS 4 1 read-write OP1OE OP1OE 12 1 read-write OP1PRS OP1PRS 8 1 read-write OP1PS OP1PS 2 1 read-write OP1TM OP1TM 3 1 read-write OP1TM1 OP1TM1 31 1 read-write OP3CON OP3_CFG Register 0x4C 32 read-write n 0x0 0xFFFFFFFF OP3EN OP3EN 0 1 read-write OP3GS OP3GS 16 3 read-write OP3NRS OP3NRS 9 1 read-write OP3NS OP3NS 4 1 read-write OP3OE OP3OE 12 1 read-write OP3PRS OP3PRS 8 1 read-write OP3PS OP3PS 2 1 read-write OP3TM OP3TM 3 1 read-write OP3TM1 OP3TM1 31 1 read-write ADC ADC ADC 0x400A8000 0x0 0x240 registers n ADC0 ADC0 Interrupt 19 ADC1 ADC1 Interrupt 20 ADC2 ADC2 Interrupt 21 ADC ADC Interrupt 22 ADCCMP0_HI ADC Comparator 0 High Comparison Value 0x18C 32 read-write n 0x0 0xFFFFFFFF cmp0_hi Enable Control Bit 0 12 read-write ADCCMP0_LO ADC Comparator 0 Low Comparison Value 0x188 32 read-write n 0x0 0xFFFFFFFF cmp0_lo Enable Control Bit 0 12 read-write ADCCMP1_HI ADC Comparator 1 High Comparison Value 0x194 32 read-write n 0x0 0xFFFFFFFF cmp1_hi Enable Control Bit 0 12 read-write ADCCMP1_LO ADC Comparator 1 Low Comparison Value 0x190 32 read-write n 0x0 0xFFFFFFFF cmp1_lo Enable Control Bit 0 12 read-write ADCCMP2_HI ADC Comparator 2 High Comparison Value 0x19C 32 read-write n 0x0 0xFFFFFFFF cmp2_hi Enable Control Bit 0 12 read-write ADCCMP2_LO ADC Comparator 2 Low Comparison Value 0x198 32 read-write n 0x0 0xFFFFFFFF cmp2_lo Enable Control Bit 0 12 read-write ADCCMP3_HI ADC Comparator 3 High Comparison Value 0x1A4 32 read-write n 0x0 0xFFFFFFFF cmp3_hi Enable Control Bit 0 12 read-write ADCCMP3_LO ADC Comparator 3 Low Comparison Value 0x1A0 32 read-write n 0x0 0xFFFFFFFF cmp3_lo Enable Control Bit 0 12 read-write ADCCMPCTL ADC Compare Control Register 0x180 32 read-write n 0x0 0xFFFFFFFF cmp0_sel Enable Control Bit 0 4 read-write cmp1_sel Enable Control Bit 4 4 read-write cmp2_sel Enable Control Bit 8 4 read-write cmp3_sel Enable Control Bit 12 4 read-write ADCCMPINTR ADC Compare INterrupt Register 0x184 32 read-write n 0x0 0xFFFFFFFF cmp0_hi Enable Control Bit 1 1 read-write cmp0_hien Enable Control Bit 17 1 read-write cmp0_lo Enable Control Bit 0 1 read-write cmp0_loen Enable Control Bit 16 1 read-write cmp1_hi Enable Control Bit 3 1 read-write cmp1_hien Enable Control Bit 19 1 read-write cmp1_lo Enable Control Bit 2 1 read-write cmp1_loen Enable Control Bit 18 1 read-write cmp2_hi Enable Control Bit 5 1 read-write cmp2_hien Enable Control Bit 21 1 read-write cmp2_lo Enable Control Bit 4 1 read-write cmp2_loen Enable Control Bit 20 1 read-write cmp3_hi Enable Control Bit 7 1 read-write cmp3_hien Enable Control Bit 23 1 read-write cmp3_lo Enable Control Bit 6 1 read-write cmp3_loen Enable Control Bit 22 1 read-write ADCCTL1 ADC Control 1 0x0 32 read-write n 0x0 0xFFFFFFFF AADCREFPD RSTEN 5 1 read-write ADCBSY RSTEN 13 1 read-write ADCBSYCHN Enable Control Bit 8 5 read-write ADCCOREPD Enable Control Bit 4 1 read-write ADCENABLE Enable Control Bit 14 1 read-write ADCPD RSTEN 7 1 read-write ADCREFSEL RSTEN 3 1 read-write ADCSHPD Enable Control Bit 6 1 read-write i25ut_oe i25ut_oe Enable Control Bit 1 1 read-write INA6_SEL INA6_SEL 22 1 read-write INA7_SEL INA7_SEL 23 1 read-write INB5_SEL INB5_SEL 29 1 read-write INB6_SEL INB6_SEL 30 1 read-write INB7_SEL INB7_SEL 31 1 read-write INTPULSEPOS Enable Control Bit 2 1 read-write RESET RSTEN 15 1 read-write vbg_oe vbg Enable Control Bit 0 1 read-write vreflo_tie_gnd vreflo_tie_gnd 16 1 read-write ADCCTL2 ADC Control 2 0x4 32 read-write n 0x0 0xFFFFFFFF clkdiv Enable Control Bit 2 4 read-write clockalwayson RSTEN 6 1 read-write dlyprediv Enable Control Bit 16 10 read-write smp_conv_delay RSTEN 11 3 read-write start_width Enable Control Bit 8 3 read-write ADCCTL3 ADC Control 3 0x8 32 read-write n 0x0 0xFFFFFFFF alias Enable Control Bit 14 2 read-write chseldlysel RSTEN 5 1 read-write converteocsel Enable Control Bit 2 1 read-write convstdlysel Enable Control Bit 0 1 read-write convstinvsel RSTEN 1 1 read-write sampledlysel Enable Control Bit 4 1 read-write shift RSTEN 24 5 read-write ADCINTFLG ADC Interrupt Flag 0x10 32 read-only n 0x0 0xFFFFFFFF ADCINT1 ADC INT FLAG 1 0 1 read-only ADCINT2 ADC INT FLAG 2 1 1 read-only ADCINT3 ADC INT FLAG 3 2 1 read-only ADCINT4 ADC INT FLAG 4 3 1 read-only ADCINT5 ADC INT FLAG 5 4 1 read-only ADCINT6 ADC INT FLAG 6 5 1 read-only ADCINT7 ADC INT FLAG 7 6 1 read-only ADCINT8 ADC INT FLAG 8 7 1 read-only ADCINT9 ADC INT FLAG 9 8 1 read-only ADCINTFLGCLR ADC Interrupt Flag Clear 0x14 32 read-write n 0x0 0xFFFFFFFF ADCINT1 ADC INT FLAG 1 Clear 0 1 read-write ADCINT2 ADC INT FLAG 2 Clear 1 1 read-write ADCINT3 ADC INT FLAG 3 Clear 2 1 read-write ADCINT4 ADC INT FLAG 4 Clear 3 1 read-write ADCINT5 ADC INT FLAG 5 Clear 4 1 read-write ADCINT6 ADC INT FLAG 6 Clear 5 1 read-write ADCINT7 ADC INT FLAG 7 Clear 6 1 read-write ADCINT8 ADC INT FLAG 8 Clear 7 1 read-write ADCINT9 ADC INT FLAG 9 Clear 8 1 read-write ADCINTOVF ADC Interrupt Overflow 0x18 32 read-only n 0x0 0xFFFFFFFF ADCINT1 ADC INT FLAG 1 0 1 read-only ADCINT2 ADC INT FLAG 2 1 1 read-only ADCINT3 ADC INT FLAG 3 2 1 read-only ADCINT4 ADC INT FLAG 4 3 1 read-only ADCINT5 ADC INT FLAG 5 4 1 read-only ADCINT6 ADC INT FLAG 6 5 1 read-only ADCINT7 ADC INT FLAG 7 6 1 read-only ADCINT8 ADC INT FLAG 8 7 1 read-only ADCINT9 ADC INT FLAG 9 8 1 read-only ADCINTOVFCLR ADC Interrupt Overflow Clear 0x1C 32 read-write n 0x0 0xFFFFFFFF ADCINT1 ADC INT FLAG 1 Clear 0 1 read-write ADCINT2 ADC INT FLAG 2 Clear 1 1 read-write ADCINT3 ADC INT FLAG 3 Clear 2 1 read-write ADCINT4 ADC INT FLAG 4 Clear 3 1 read-write ADCINT5 ADC INT FLAG 5 Clear 4 1 read-write ADCINT6 ADC INT FLAG 6 Clear 5 1 read-write ADCINT7 ADC INT FLAG 7 Clear 6 1 read-write ADCINT8 ADC INT FLAG 8 Clear 7 1 read-write ADCINT9 ADC INT FLAG 9 Clear 8 1 read-write ADCINTSOCSEL1 ADC Interrupt SOC Selection 1 0x50 32 read-write n 0x0 0xFFFFFFFF ADCINTSOCSEL2 ADC Interrupt SOC Selection 2 0x54 32 read-write n 0x0 0xFFFFFFFF ADCRESULT0 Conversion Result Buffer 0 0x200 32 read-only n 0x0 0xFFFFFFFF RESULT Enable Control Bit 0 12 read-only ADCRESULT1 0x204 -1 read-write n ADCRESULT10 0x228 -1 read-write n ADCRESULT11 0x22C -1 read-write n ADCRESULT12 0x230 -1 read-write n ADCRESULT13 0x234 -1 read-write n ADCRESULT14 0x238 -1 read-write n ADCRESULT15 0x23C -1 read-write n ADCRESULT2 0x208 -1 read-write n ADCRESULT3 0x20C -1 read-write n ADCRESULT4 0x210 -1 read-write n ADCRESULT5 0x214 -1 read-write n ADCRESULT6 0x218 -1 read-write n ADCRESULT7 0x21C -1 read-write n ADCRESULT8 0x220 -1 read-write n ADCRESULT9 0x224 -1 read-write n ADCSAMPLEMODE ADC Sampling Mode 0x48 32 read-write n 0x0 0xFFFFFFFF SIMULEN0 Enable Control Bit 0 1 read-write SIMULEN12 RSTEN 6 1 read-write SIMULEN14 Enable Control Bit 7 1 read-write SIMULEN1O Enable Control Bit 5 1 read-write SIMULEN2 RSTEN 1 1 read-write SIMULEN4 Enable Control Bit 2 1 read-write SIMULEN6 Enable Control Bit 3 1 read-write SIMULEN8 RSTEN 4 1 read-write ADCSOC0CTL ADC SOC0 Control 0x80 32 read-write n 0x0 0xFFFFFFFF ACQPS Enable Control Bit 0 6 read-write CHSEL RSTEN 6 4 read-write INDLY RSTEN 16 8 read-write TRIGSEL Enable Control Bit 11 5 read-write ADCSOC10CTL 0xA8 -1 read-write n ADCSOC11CTL 0xAC -1 read-write n ADCSOC12CTL 0xB0 -1 read-write n ADCSOC13CTL 0xB4 -1 read-write n ADCSOC14CTL 0xB8 -1 read-write n ADCSOC15CTL 0xBC -1 read-write n ADCSOC1CTL 0x84 -1 read-write n ADCSOC2CTL 0x88 -1 read-write n ADCSOC3CTL 0x8C -1 read-write n ADCSOC4CTL ADC SOC4 Control 0x90 32 read-write n 0x0 0xFFFFFFFF ACQPS Enable Control Bit 0 6 read-write CHSEL RSTEN 6 4 read-write TRIGSEL Enable Control Bit 11 5 read-write ADCSOC5CTL 0x94 -1 read-write n ADCSOC6CTL 0x98 -1 read-write n ADCSOC7CTL 0x9C -1 read-write n ADCSOC8CTL 0xA0 -1 read-write n ADCSOC9CTL 0xA4 -1 read-write n ADCSOCFLG1 ADC SOC Flag 1 0x60 32 read-only n 0x0 0xFFFFFFFF ADCSOCFRC1 ADC SOC Flag Force 1 0x68 32 read-write n 0x0 0xFFFFFFFF ADCSOCOVF1 ADC SOC Overflow 1 0x70 32 read-only n 0x0 0xFFFFFFFF ADCSOCOVFCLR1 ADC SOC Overflow Clear 1 0x78 32 read-write n 0x0 0xFFFFFFFF ADCTRIM ADCTRIM Register 0x100 32 read-write n 0x4C488080 0xFFFFFFFF itrim itrim 16 4 read-write meas_i meas_i 22 1 read-write mode2 mode2 29 1 read-write ntrim ntrim 23 1 read-write offtrim offtrim 8 8 read-write reftrim reftrim 0 8 read-write tadj tadj 27 1 read-write tc tc 24 3 read-write trim_opt2 trim_opt2 28 1 read-write vol_sel vol_sel 30 1 read-write INTSEL1N2 ADC Interrupt 1 and 2 Selection 0x20 32 read-write n 0x0 0xFFFFFFFF INT1CONT Enable Control Bit 6 1 read-write INT1E RSTEN 5 1 read-write INT1SEL Enable Control Bit 0 5 read-write INT2CONT Enable Control Bit 14 1 read-write INT2E RSTEN 13 1 read-write INT2SEL Enable Control Bit 8 5 read-write INTSEL3N4 ADC Interrupt 3 and 4 Selection 0x24 32 read-write n 0x0 0xFFFFFFFF INT3CONT Enable Control Bit 6 1 read-write INT3E RSTEN 5 1 read-write INT3SEL Enable Control Bit 0 5 read-write INT4CONT Enable Control Bit 14 1 read-write INT4E RSTEN 13 1 read-write INT4SEL Enable Control Bit 8 5 read-write INTSEL5N6 ADC Interrupt 5 and 6 Selection 0x28 32 read-write n 0x0 0xFFFFFFFF INT5CONT Enable Control Bit 6 1 read-write INT5E RSTEN 5 1 read-write INT5SEL Enable Control Bit 0 5 read-write INT6CONT Enable Control Bit 14 1 read-write INT6E RSTEN 13 1 read-write INT6SEL Enable Control Bit 8 5 read-write INTSEL7N8 ADC Interrupt 7 and 8 Selection 0x2C 32 read-write n 0x0 0xFFFFFFFF INT7CONT Enable Control Bit 6 1 read-write INT7E RSTEN 5 1 read-write INT7SEL Enable Control Bit 0 5 read-write INT8CONT Enable Control Bit 14 1 read-write INT8E RSTEN 13 1 read-write INT8SEL Enable Control Bit 8 5 read-write INTSEL9N10 ADC Interrupt 9 and 10 Selection 0x30 32 read-write n 0x0 0xFFFFFFFF INT10CONT Enable Control Bit 14 1 read-write INT10E RSTEN 13 1 read-write INT10SEL Enable Control Bit 8 5 read-write INT9CONT Enable Control Bit 6 1 read-write INT9E RSTEN 5 1 read-write INT9SEL Enable Control Bit 0 5 read-write SOCPRICTL ADC SOC Priority Control 0x40 32 read-write n 0x0 0xFFFFFFFF RRPOINTER RSTEN 5 6 read-only SOCPRIORITY Enable Control Bit 0 5 read-write CHIPCTL CHIPCTL CHIPCTL 0x40081000 0x0 0xC04 registers n IWDT IWDT Interrupt 15 CHIP_KEY CHIP_KEY Register 0x5C 32 read-write n 0x0 0xFFFFFFFF KEY KEY 0 32 read-write CLKCFG0 CLKCFG0 Register 0x4 32 read-write n 0x0 0xFFFFFFFF PLLDIV PLLDIV 4 4 read-write PLLMUL PLLMUL 10 2 read-write PLLSRC PLLSRC 0 1 read-write XCLKDIV XCLKDIV 28 3 read-write XCLKINSEL XCLKINSEL 20 2 read-write XCLKSEL XCLKSEL 24 4 read-write CLKCFG1 CLKCFG1 Register 0x8 32 read-write n 0x1 0xFFFFFFFF SYSCLKLOCK SYSCLKLOCK 4 1 read-only SYSCLKSEL SYSCLKSEL 0 2 read-write SYSTICKSEL SYSTICKSEL 8 2 read-write CLKCFG2 CLKCFG2 Register 0xC 32 read-write n 0x0 0xFFFFFFFF HDIV HDIV 0 8 read-write MTDIV MTDIV 8 4 read-write PDIV01 PDIV01 16 4 read-write PDIV023 PDIV023 24 4 read-write CLKCTRL CLKCTRL Register 0x0 32 read-write n 0x1000 0xFFFFFFFF OSCDETEN OSCDETEN 1 1 read-write OSCEN OSCEN 0 1 read-write OSCGAIN OSCGAIN 4 2 read-write OSCRFEN OSCRFEN 6 1 read-write OSCSRB_SEL OSCSRB_SEL 8 2 read-write OSCSTB OSCSTB 11 1 read-only OSCSTOP OSCSTOP 2 1 read-only OSCXCKEN OSCXCKEN 7 1 read-write PLLEN PLLEN 28 1 read-write PLLLOCK PLLLOCK 30 1 read-only RCHEN RCHEN 12 1 read-write RCHPT RCHPT 24 4 read-write RCHSTB RCHSTB 14 1 read-only RCHTRIM RCHTRIM 16 8 read-write CLKEN_H01 CLKEN_H01 Register 0x10 32 read-write n 0x7 0xFFFFFFFF PA_CLKEN PA_CLKEN 0 1 read-write PB_CLKEN PB_CLKEN 1 1 read-write PC_CLKEN PC_CLKEN 2 1 read-write CLKEN_H23 CLKEN_H23 Register 0x14 32 read-write n 0x0 0xFFFFFFFF COPROC_CLKEN COPROC_CLKEN 0 1 read-write CLKEN_P01 CLKEN_P01 Register 0x18 32 read-write n 0x0 0xFFFFFFFF DMA_CLKEN DMA_CLKEN 6 1 read-write ERU_CLKEN ERU_CLKEN 3 1 read-write I2C_CLKEN I2C_CLKEN 23 1 read-write PPU_CLKEN PPU_CLKEN 2 1 read-write SSP_CLKEN SSP_CLKEN 24 1 read-write UART0_CLKEN UART0_CLKEN 16 1 read-write UART1_CLKEN UART1_CLKEN 17 1 read-write UART2_CLKEN UART2_CLKEN 18 1 read-write CLKEN_P23 CLKEN_P23 Register 0x1C 32 read-write n 0x0 0xFFFFFFFF ACMP_OPA_CLKEN ACMP_OPA_CLKEN 10 1 read-write ADC_CLKEN ADC_CLKEN 8 1 read-write PWMTOP0_CLKEN PWMTOP0_CLKEN 4 1 read-write PWMTOP1_CLKEN PWMTOP1_CLKEN 5 1 read-write TIMERTOP0_CLKEN TIMERTOP0_CLKEN 12 1 read-write TIMERTOP1_CLKEN TIMERTOP1_CLKEN 13 1 read-write TIMERTOP6_CLKEN TIMERTOP6_CLKEN 15 1 read-write INTMASK INTMASK Register 0x50 32 read-write n 0xFFFFFFFF 0xFFFFFFFF CVM_MASK CVM_MASK 2 1 read-write DEBUG_VALID_MASK DEBUG_VALID_MASK 12 1 read-write IO_WAKEUP_MASK IO_WAKEUP_MASK 11 1 read-write IWDTRST_MASK IWDTRST_MASK 7 1 read-write LOCKUP_MASK LOCKUP_MASK 9 1 read-write LVD_MASK LVD_MASK 4 1 read-write LVR_MASK LVR_MASK 3 1 read-write NRST_MASK NRST_MASK 5 1 read-write OSCEN_CFGERR_MASK OSCEN_CFGERR_MASK 28 1 read-write OSC_MISS_MASK OSC_MISS_MASK 18 1 read-write PLLEN_CFGERR_MASK PLLEN_CFGERR_MASK 29 1 read-write PLLSRC_CFGERR_MASK PLLSRC_CFGERR_MASK 25 1 read-write PLL_MISS_MASK PLL_MISS_MASK 20 1 read-write POC_MASK POC_MASK 1 1 read-write POR_MASK POR_MASK 0 1 read-write RCHEN_CFGERR_MASK RCHEN_CFGERR_MASK 27 1 read-write RCH_MISS_MASK RCH_MISS_MASK 16 1 read-write SCLKSEL_CFGERR_MASK SCLKSEL_CFGERR_MASK 24 1 read-write SRST_MASK SRST_MASK 8 1 read-write SYSCLKMUX_ERR_MASK SYSCLKMUX_ERR_MASK 22 1 read-write SYSCLKMUX_RST_MASK SYSCLKMUX_RST_MASK 10 1 read-write WDTRST_MASK WDTRST_MASK 6 1 read-write IWDT_CFG IWDT_CFG Register 0x40 32 read-write n 0x0 0xFFFFFFFF WINEN WINEN 0 1 read-write WINSEL WINSEL 8 1 read-write IWDT_CLKDIV IWDT_CLKDIV Register 0x44 32 read-write n 0x0 0xFFFFFFFF CLKDIV CLKDIV 0 4 read-write IWDT_CTRL IWDT_CTRL Register 0x3C 32 write-only n 0x0 0xFFFFFFFF CONTROL CONTROL 0 32 write-only IWDT_RLD IWDT_RLD Register 0x48 32 read-write n 0xFFFF 0xFFFFFFFF RLD RLD 0 16 read-write IWDT_STATUS IWDT_STATUS Register 0x4C 32 read-only n 0x0 0xFFFFFFFF CNT CNT 0 16 read-only INTR INTR 16 1 read-only UPDATING UPDATING 31 1 read-only POWER_CTRL POWER_CTRL Register 0x30 32 read-write n 0x9008 0xFFFFFFFF CVMEN CVMEN 19 1 read-write CVREN CVREN 9 1 read-write DEBUG_NOSLEEP DEBUG_NOSLEEP 3 1 read-write FLASH_CG FLASH_CG 4 1 read-write FLASH_LP FLASH_LP 5 1 read-write IPE IPE 0 1 read-write LOOKUPREN LOOKUPREN 10 1 read-write LVDEN LVDEN 20 1 read-write LVES LVES 21 1 read-write LVLS LVLS 22 3 read-write LVREN LVREN 15 1 read-write LVRS LVRS 16 2 read-write MVRPS MVRPS 12 1 read-write MVRSEL MVRSEL 13 1 read-write POCREN POCREN 8 1 read-write SRAM_CG SRAM_CG 6 1 read-write SYSCLK_DCTEN SYSCLK_DCTEN 2 1 read-write SYSCLK_MUX_RSTEN SYSCLK_MUX_RSTEN 1 1 read-write VTSEL VTSEL 28 2 read-write VTSEN VTSEN 27 1 read-write REMAP_CTRL REMAP_CTRL Register 0x38 32 read-write n 0x1 0xFFFFFFFF DEBUG_USEASFUNC DEBUG_USEASFUNC 12 1 read-write REMAP REMAP 0 1 read-write REMAP_KEY REMAP_KEY 16 16 read-write SRST_USEASFUNC SRST_USEASFUNC 8 1 read-write SYSRESET_OUTEN SYSRESET_OUTEN 9 1 read-write SYSRESET_OUTSEL SYSRESET_OUTSEL 10 1 read-write SRST_REQ_H01 SRST_REQ_H01 Register 0x20 32 read-write n 0xFFFFFFFF 0xFFFFFFFF PA_SRST_REQ PA_SRST_REQ 0 1 read-write PB_SRST_REQ PB_SRST_REQ 2 1 read-write PC_SRST_REQ PC_SRST_REQ 3 1 read-write SRST_REQ_H23 SRST_REQ_H23 Register 0x24 32 read-write n 0xFFFFFFFF 0xFFFFFFFF COPROC_SRST_REQ COPROC_SRST_REQ 0 1 read-write SRST_REQ_P01 SRST_REQ_P01 Register 0x28 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DMA_SRST_REQ DMA_SRST_REQ 6 1 read-write ERU_SRST_REQ ERU_SRST_REQ 3 1 read-write I2C_SRST_REQ I2C_SRST_REQ 23 1 read-write PPU_SRST_REQ PPU_SRST_REQ 2 1 read-write SSP_SRST_REQ SSP_SRST_REQ 24 1 read-write UART0_SRST_REQ UART0_SRST_REQ 16 1 read-write UART1_SRST_REQ UART1_SRST_REQ 17 1 read-write UART2_SRST_REQ UART2_SRST_REQ 18 1 read-write SRST_REQ_P23 SRST_REQ_P23 Register 0x2C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF ACMP_OPA_SRST_REQ ACMP_OPA_SRST_REQ 10 1 read-write ADC_SRST_REQ ADC_SRST_REQ 8 1 read-write PWMTOP0_SRST_REQ PWMTOP0_SRST_REQ 4 1 read-write PWMTOP1_SRST_REQ PWMTOP1_SRST_REQ 5 1 read-write TIMERTOP0_SRST_REQ TIMERTOP0_SRST_REQ 12 1 read-write TIMERTOP1_SRST_REQ TIMERTOP1_SRST_REQ 13 1 read-write TIMERTOP6_SRST_REQ TIMERTOP6_SRST_REQ 15 1 read-write STATUS0 STATUS0 Register 0x54 32 read-write n 0x0 0xFFFFFFFF CVM_EVENT CVM_EVENT 2 1 read-write DEBUG_VALID_EVENT DEBUG_VALID_EVENT 12 1 read-write IO_WAKEUP_EVENT IO_WAKEUP_EVENT 11 1 read-write IWDTRST_EVENT IWDTRST_EVENT 7 1 read-write LOCKUP_EVENT LOCKUP_EVENT 9 1 read-write LVD_EVENT LVD_EVENT 4 1 read-write LVR_EVENT LVR_EVENT 3 1 read-write NRST_EVENT NRST_EVENT 5 1 read-write OSCEN_CFGERR_EVENT OSCEN_CFGERR_EVENT 28 1 read-write OSC_MISS_EVENT OSC_MISS_EVENT 18 1 read-write PLLEN_CFGERR_EVENT PLLEN_CFGERR_EVENT 29 1 read-write PLLSRC_CFGERR_EVENT PLLSRC_CFGERR_EVENT 25 1 read-write PLL_MISS_MASK PLL_MISS_MASK 20 1 read-write POC_EVENT POC_EVENT 1 1 read-write POR_EVENT POR_EVENT 0 1 read-write RCHEN_CFGERR_EVENT RCHEN_CFGERR_EVENT 27 1 read-write RCH_MISS_EVENT RCH_MISS_MEVENT 16 1 read-write SCLKSEL_CFGERR_EVENT SCLKSEL_CFGERR_EVENT 24 1 read-write SRST_EVENT SRST_EVENT 8 1 read-write SYSCLKMUX_ERR_EVENT SYSCLKMUX_ERR_EVENT 22 1 read-write SYSCLKMUX_RST_EVENT SYSCLKMUX_RST_EVENT 10 1 read-write WDTRST_EVENT WDTRST_EVENT 6 1 read-write STATUS1 STATUS1 Register 0x58 32 read-only n 0x0 0xFFFFFFFF BGRFLAG BGRFLAG 11 1 read-only CVMFLAG CVMFLAG 9 1 read-only IWDT_INTR IWDT_INTR 13 1 read-only LVRFLAG LVRFLAG 7 1 read-only OSCSTOP OSCSTOP 0 1 read-only PLLLOCK PLLLOCK 5 1 read-only RCHSTB RCHSTB 3 1 read-only VERSION VERSION Register 0xC00 32 read-only n 0xD6930 0xFFFFFFFF WAKEUP_CTRL WAKEUP_CTRL Register 0x34 32 read-write n 0x0 0xFFFFFFFF DEBUG_WAKEUPEN DEBUG_WAKEUPEN 4 1 read-write IO_WAKEUPEN IO_WAKEUPEN 0 1 read-write IWDT_WAKEUPEN IWDT_WAKEUPEN 2 1 read-write LVD_WAKEUPEN LVD_WAKEUPEN 8 1 read-write COPROC COPROC COPROC 0x40020000 0x0 0xB0 registers n COPROC COPROC Interrupt 12 CRC_CTRL CRC_CTRL 0x60 32 read-write n 0x0 0xFFFFFFFF CRC_BYTE CRC_BYTE 8 2 read-write CRC_GPS CRC_GPS 24 2 read-write CRC_LM CRC_LM 16 1 read-write RESET RESET 0 1 write-only RESET_CRC RESET_CRC 1 1 write-only CRC_DATA CRC_DATA 0x64 32 read-write n 0x0 0xFFFFFFFF CRC_RESULT CRC_RESULT 0x68 32 read-write n 0x0 0xFFFFFFFF DIV_AHI DIV_AHI 0x38 32 read-write n 0x0 0xFFFFFFFF DIV_ALO DIV_ALO 0x34 32 read-write n 0x0 0xFFFFFFFF DIV_B DIV_B 0x3C 32 read-write n 0x0 0xFFFFFFFF DIV_CTRL DIV_CTRL Register 0x30 32 read-write n 0xFFFFFFFF 0x0 divider_32bit divider_32bit 8 1 read-write div_by_0 div_by_0 24 1 read-write div_reset div_reset 0 1 write-only DIV_QUOTHI DIV_QUOTHI 0x44 32 read-write n 0x0 0xFFFFFFFF DIV_QUOTLO DIV_QUOTLO 0x40 32 read-write n 0x0 0xFFFFFFFF DIV_REM DIV_REM 0x48 32 read-write n 0x0 0xFFFFFFFF MULTA MULTA Register 0x8 32 read-write n 0xFFFFFFFF 0x0 MULTA_ADD MULTA_ADD Register 0x10 32 read-write n 0x0 0xFFFFFFFF MULTA_SUB MULTA_SUB Register 0x18 32 read-write n 0xFFFFFFFF 0x0 MULTB MULTB 0xC 32 read-write n 0x0 0xFFFFFFFF MULTB_ADD MULTB_ADD Register 0x14 32 read-write n 0x0 0xFFFFFFFF MULTB_SUB MULTB_SUB 0x1C 32 read-write n 0x0 0xFFFFFFFF MULT_CTRL MULT_CTRL Register 0x0 32 read-write n 0x0 0xFFFFFFFF carry carry 9 1 read-write cr_intr_en cr_intr_en 13 1 read-write mult_only mult_only 19 1 read-write mult_signed mult_signed 31 1 read-write overflow overflow 8 1 read-write ov_intr_en ov_intr_en 12 1 read-write reset_mult reset_mult 0 1 write-only reset_result reset_result 1 1 write-only shift_en shift_en 17 1 read-write shift_imm shift_imm 16 1 read-write shift_sel shift_sel 18 1 read-write MULT_RESULHI MULT_RESULHI Register 0x24 32 read-write n 0x0 0xFFFFFFFF MULT_RESULLO MULT_RESULLO Register 0x20 32 read-write n 0x0 0xFFFFFFFF SHIFT_NUM SHIFT_NUM Register 0x4 32 read-write n 0x0 0xFFFFFFFF DMA DMA module DMA 0x40086000 0x0 0xD00 registers n DMA DMA Interrupt 11 ACTIVE Active Register 0xC8 32 read-only n 0x0 0xFFFFFFFF ALT_BASE_PTR Channel Standby Control Base Address Pointer Register 0x8 32 read-only n 0x10 0xFFFFFFFF BASE_PTR Channel Control Base Address Pointer Register 0x4 32 read-write n 0x0 0xFFFFFFFF BUS_ERR Bus Error Register 0xD4 32 read-write n 0x0 0xFFFFFFFF CFG DMA Configure Register 0x0 32 read-write n 0x0 0xFFFFFFFF ENABLE DMA Transmit Size 0 1 read-write PORT DMA Transmit Size 1 3 read-write RESET DMA Transmit Size 31 1 read-write CFG_ERR Configure Error Register 0xD0 32 read-write n 0x0 0xFFFFFFFF CTRL0 DMA Channel 0 Control Register 0x20 32 read-write n 0x0 0xFFFFFFFF CHNL_BUSERR_INTREN DMA Transmit Size 24 1 read-write CHNL_CFGERR_INTREN DMA Transmit Size 25 1 read-write CHNL_DMADONE_INTREN DMA Transmit Size 28 1 read-write CHNL_ENABLE DMA Transmit Size 0 1 read-write CHNL_PRIORITY DMA Transmit Size 5 1 read-write CHNL_PRI_ALT DMA Transmit Size 2 1 read-write CHNL_REQ0_MASK DMA Transmit Size 15 1 read-write CHNL_REQ0_SEL DMA Transmit Size 8 5 read-write CHNL_REQ1_MASK DMA Transmit Size 23 1 read-write CHNL_REQ1_SEL DMA Transmit Size 16 5 read-write CHNL_USE_BURST DMA Transmit Size 4 1 read-write CTRL1 DMA Channel 1 Control Register 0x24 32 read-write n 0x0 0xFFFFFFFF CHNL_BUSERR_INTREN DMA Transmit Size 24 1 read-write CHNL_CFGERR_INTREN DMA Transmit Size 25 1 read-write CHNL_DMADONE_INTREN DMA Transmit Size 28 1 read-write CHNL_ENABLE DMA Transmit Size 0 1 read-write CHNL_PRIORITY DMA Transmit Size 5 1 read-write CHNL_PRI_ALT DMA Transmit Size 2 1 read-write CHNL_REQ0_MASK DMA Transmit Size 15 1 read-write CHNL_REQ0_SEL DMA Transmit Size 8 5 read-write CHNL_REQ1_MASK DMA Transmit Size 23 1 read-write CHNL_REQ1_SEL DMA Transmit Size 16 5 read-write CHNL_USE_BURST DMA Transmit Size 4 1 read-write CTRL2 DMA Channel 2 Control Register 0x28 32 read-write n 0x0 0xFFFFFFFF CHNL_BUSERR_INTREN DMA Transmit Size 24 1 read-write CHNL_CFGERR_INTREN DMA Transmit Size 25 1 read-write CHNL_DMADONE_INTREN DMA Transmit Size 28 1 read-write CHNL_ENABLE DMA Transmit Size 0 1 read-write CHNL_PRIORITY DMA Transmit Size 5 1 read-write CHNL_PRI_ALT DMA Transmit Size 2 1 read-write CHNL_REQ0_MASK DMA Transmit Size 15 1 read-write CHNL_REQ0_SEL DMA Transmit Size 8 5 read-write CHNL_REQ1_MASK DMA Transmit Size 23 1 read-write CHNL_REQ1_SEL DMA Transmit Size 16 5 read-write CHNL_USE_BURST DMA Transmit Size 4 1 read-write CTRL3 DMA Channel 3 Control Register 0x2C 32 read-write n 0x0 0xFFFFFFFF CHNL_BUSERR_INTREN DMA Transmit Size 24 1 read-write CHNL_CFGERR_INTREN DMA Transmit Size 25 1 read-write CHNL_DMADONE_INTREN DMA Transmit Size 28 1 read-write CHNL_ENABLE DMA Transmit Size 0 1 read-write CHNL_PRIORITY DMA Transmit Size 5 1 read-write CHNL_PRI_ALT DMA Transmit Size 2 1 read-write CHNL_REQ0_MASK DMA Transmit Size 15 1 read-write CHNL_REQ0_SEL DMA Transmit Size 8 5 read-write CHNL_REQ1_MASK DMA Transmit Size 23 1 read-write CHNL_REQ1_SEL DMA Transmit Size 16 5 read-write CHNL_USE_BURST DMA Transmit Size 4 1 read-write CTRL4 DMA Channel 4 Control Register 0x30 32 read-write n 0x0 0xFFFFFFFF CHNL_BUSERR_INTREN DMA Transmit Size 24 1 read-write CHNL_CFGERR_INTREN DMA Transmit Size 25 1 read-write CHNL_DMADONE_INTREN DMA Transmit Size 28 1 read-write CHNL_ENABLE DMA Transmit Size 0 1 read-write CHNL_PRIORITY DMA Transmit Size 5 1 read-write CHNL_PRI_ALT DMA Transmit Size 2 1 read-write CHNL_REQ0_MASK DMA Transmit Size 15 1 read-write CHNL_REQ0_SEL DMA Transmit Size 8 5 read-write CHNL_REQ1_MASK DMA Transmit Size 23 1 read-write CHNL_REQ1_SEL DMA Transmit Size 16 5 read-write CHNL_USE_BURST DMA Transmit Size 4 1 read-write CTRL5 DMA Channel 5 Control Register 0x34 32 read-write n 0x0 0xFFFFFFFF CHNL_BUSERR_INTREN DMA Transmit Size 24 1 read-write CHNL_CFGERR_INTREN DMA Transmit Size 25 1 read-write CHNL_DMADONE_INTREN DMA Transmit Size 28 1 read-write CHNL_ENABLE DMA Transmit Size 0 1 read-write CHNL_PRIORITY DMA Transmit Size 5 1 read-write CHNL_PRI_ALT DMA Transmit Size 2 1 read-write CHNL_REQ0_MASK DMA Transmit Size 15 1 read-write CHNL_REQ0_SEL DMA Transmit Size 8 5 read-write CHNL_REQ1_MASK DMA Transmit Size 23 1 read-write CHNL_REQ1_SEL DMA Transmit Size 16 5 read-write CHNL_USE_BURST DMA Transmit Size 4 1 read-write DONE Done Register 0xCC 32 read-write n 0x0 0xFFFFFFFF REQUEST_ON DMA Request Wait Status Register 0xC4 32 read-only n 0x0 0xFFFFFFFF STATUS DMA Status Control Register 0xC0 32 read-only n 0x0 0xFFFFFFFF CHNL_NUM_MINUS1 Busy 16 5 read-only CREQ_NUM_MINUS1 Busy 8 5 read-only ENABLE Package Size 0 1 read-only STATE Transmit Size 4 4 read-only SW_REQ Software Request Register 0xC 32 write-only n 0x0 0xFFFFFFFF VERSION DMA Version Register 0xC00 32 read-only n 0xD6510 0xFFFFFFFF ERU ERU ERU 0x40083000 0x0 0x30 registers n ERU0 ERU0 Interrupt 28 ERU1 ERU1 Interrupt 29 ERU2 ERU2 Interrupt 30 ERU3 ERU3 Interrupt 31 EXICON0 ERU Input Control Register 0 0x10 32 read-write n 0x0 0xFFFFFFFF APOL The polarity of the input A choice 18 1 read-write BPOL The polarity of the input B choice 19 1 read-write ERSOSEL ERS0 input source Selecet 16 2 read-write FE ETL0 Falling Edge Test Enable 3 1 read-write FL ETL0 status flag 8 1 read-write LD ETL0 Reconstruction of the Status Flag Level Detection 1 1 read-write OCS ETL0 Output Trigger Pulse Output Channel Choice 4 3 read-write PE ETL0 Output Trigger Pulse Enable 0 1 read-write RE ETL0 Rising Edge Test Enable 2 1 read-write EXICON1 0x14 -1 read-write n EXICON2 0x18 -1 read-write n EXICON3 0x1C -1 read-write n EXISEL ERU Input Select Register 0x0 32 read-write n 0x0 0xFFFFFFFF in0_sela A0 Event Source Select 0 3 read-write in0_selb B0 Event Source Select 4 3 read-write in1_sela A1 Event Source Select 8 3 read-write in1_selb B1 Event Source Select 12 3 read-write in2_sela A2 Event Source Select 16 3 read-write in2_selb B2 Event Source Select 20 3 read-write in3_sela A3 Event Source Select 24 3 read-write in3_selb B3 Event Source Select 28 3 read-write EXOCON0 ERU Output Control Register 0 0x20 32 read-write n 0x0 0xFFFFFFFF GEEN Door control events enable 2 1 read-write GP Model test results of gating options 4 2 read-write IPEN0 ETL0 Model test enable 16 1 read-write IPEN1 ETL1 Model test enable 17 1 read-write IPEN2 ETL2 Model test enable 18 1 read-write IPEN3 ETL3 Model test enable 19 1 read-write ISS Internal trigger source choice 0 2 read-write PDR Model test results flag 3 1 read-only EXOCON1 0x24 -1 read-write n EXOCON2 0x28 -1 read-write n EXOCON3 0x2C -1 read-write n IAP IAP IAP 0x40088000 0x0 0x50 registers n IAP IAP Interrupt 13 ADDR Flash Address Register 0x10 32 read-write n 0x0 0xFFFFFFFF BTADDR BOOT Partition address information Register 0x3C 32 read-only n 0x0 0xFFFFFFFF EDADDR Protect Interrupt Clear 16 16 read-only STADDR Complete Operation Clear 0 16 read-only CCLR Flash Control Clear Register 0x4 32 write-only n 0x0 0xFFFFFFFF BOOTKEYEN BOOTKEYEN 3 1 write-only PAGEEN PAGEEN 2 1 write-only PROGEN PROGEN 1 1 write-only USR1KEYEN USR1KEYEN 4 1 write-only USR2KEYEN USR2KEYEN 5 1 write-only CFG Flash Configure Register 0xC 32 read-write n 0x0 0xFFFFFFFF PREFETCHEN PREFETCHEN 3 1 read-write READCFG READCFG 0 3 read-write CSET Flash Control Set Register 0x0 32 write-only n 0x0 0xFFFFFFFF BOOTKEYEN BOOTKEYEN 3 1 write-only OPSTART OPSTART 0 1 write-only PAGEEN PAGEEN 2 1 write-only PROGEN PROGEN 1 1 write-only USR1KEYEN USR1KEYEN 4 1 write-only USR2KEYEN USR2KEYEN 5 1 write-only CTRL Flash Control Status Register 0x8 32 read-only n 0x0 0xFFFFFFFF BOOTKEYEN BOOTKEYEN 3 1 read-only PAGEEN PAGEEN 2 1 read-only PROGEN PROGEN 1 1 read-only USR1KEYEN USR1KEYEN 4 1 read-only USR2KEYEN USR2KEYEN 5 1 read-only DATA Flash Data Register 0x14 32 read-write n 0x0 0xFFFFFFFF FEED Flash feed Register 0x18 32 write-only n 0x0 0xFFFFFFFF ICR Flash Interrupt Clear Register 0x24 32 write-only n 0x0 0xFFFFFFFF COMPCLR Complete Operation Clear 0 1 write-only ERRORCLR Error Interrupt Clear 2 1 write-only PROTCLR Protect Interrupt Clear 1 1 write-only IEN Flash Interrupt Enable Register 0x1C 32 read-write n 0x0 0xFFFFFFFF COMPINTEN Complete Operation Interrupt Enable 0 1 read-write ERRINTEN Error Interrupt Enable 2 1 read-write PROTINTEN Protect Interrupt Enable 1 1 read-write ISR Flash Interrupt Status Register 0x20 32 read-only n 0x0 0xFFFFFFFF COMPLETE Complete Operation Status 0 1 read-only ERROR Error Interrupt Status 2 1 read-only PROTECT Protect Interrupt Status 1 1 read-only KEY1 Flash Key1 Match Register 0x2C 32 write-only n 0x0 0xFFFFFFFF KEY2 Flash Key2 Match Register 0x30 32 write-only n 0x0 0xFFFFFFFF KEY3 Flash Key3 Match Register 0x34 32 write-only n 0x0 0xFFFFFFFF KEY4 Flash Key4 Match Register 0x38 32 write-only n 0x0 0xFFFFFFFF STATUS Flash Status Register 0x28 32 read-only n 0x0 0xFFFFFFFF BOOTCRCOK BOOT partition CRC check Status 24 1 read-only BOOTKEYOK BOOT key matching Status 16 1 read-only BOOTPAREN BOOT partition Status 8 1 read-only USR1CRCOK USR1 partition CRC check Status 25 1 read-only USR1KEYOK USR1 key matching Status 17 1 read-only USR1PAREN USR1 partition Status 9 1 read-only USR2CRCOK USR2 partition CRC check Status 26 1 read-only USR2KEYOK USR2 key matching Status 18 1 read-only USR2PAREN USR1 partition Status 10 1 read-only U1ADDR User1 Partition address information Register 0x40 32 read-only n 0x0 0xFFFFFFFF EDADDR Protect Interrupt Clear 16 16 read-only STADDR Complete Operation Clear 0 16 read-only U2ADDR User2 Partition address information Register 0x44 32 read-only n 0x0 0xFFFFFFFF EDADDR Protect Interrupt Clear 16 16 read-only STADDR Complete Operation Clear 0 16 read-only PA PA P0RT 0x40000000 0x0 0xC04 registers n PA PA Interrupt 16 CFG0 PORT Control Register 0x0 32 read-write n 0x0 0xFFFFFFFF ANAEN ANAEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG1 0x4 -1 read-write n CFG10 0x28 -1 read-write n CFG11 0x2C -1 read-write n CFG12 0x30 -1 read-write n CFG13 0x34 -1 read-write n CFG14 0x38 -1 read-write n CFG15 0x3C -1 read-write n CFG16 0x40 -1 read-write n CFG17 0x44 -1 read-write n CFG18 0x48 -1 read-write n CFG19 0x4C -1 read-write n CFG2 0x8 -1 read-write n CFG20 0x50 -1 read-write n CFG21 0x54 -1 read-write n CFG22 0x58 -1 read-write n CFG23 0x5C -1 read-write n CFG24 0x60 -1 read-write n CFG25 0x64 -1 read-write n CFG26 0x68 -1 read-write n CFG27 0x6C -1 read-write n CFG28 0x70 -1 read-write n CFG29 0x74 -1 read-write n CFG3 0xC -1 read-write n CFG30 0x78 -1 read-write n CFG31 0x7C -1 read-write n CFG4 0x10 -1 read-write n CFG5 0x14 -1 read-write n CFG6 0x18 -1 read-write n CFG7 0x1C -1 read-write n CFG8 0x20 -1 read-write n CFG9 0x24 -1 read-write n GCFG0 Global Configuration Register 0 0xD8 32 write-only n 0x0 0xFFFFFFFF GMASK0 GMASK0 0 1 write-only GMASK1 GMASK1 1 1 write-only GMASK10 GMASK10 10 1 write-only GMASK11 GMASK11 11 1 write-only GMASK12 GMASK12 12 1 write-only GMASK13 GMASK13 13 1 write-only GMASK14 GMASK14 14 1 write-only GMASK15 GMASK15 15 1 write-only GMASK16 GMASK16 16 1 write-only GMASK17 GMASK17 17 1 write-only GMASK18 GMASK18 18 1 write-only GMASK19 GMASK19 19 1 write-only GMASK2 GMASK2 2 1 write-only GMASK20 GMASK20 20 1 write-only GMASK21 GMASK21 21 1 write-only GMASK22 GMASK22 22 1 write-only GMASK23 GMASK23 23 1 write-only GMASK24 GMASK24 24 1 write-only GMASK25 GMASK25 25 1 write-only GMASK26 GMASK26 26 1 write-only GMASK27 GMASK27 27 1 write-only GMASK28 GMASK28 28 1 write-only GMASK29 GMASK29 29 1 write-only GMASK3 GMASK3 3 1 write-only GMASK30 GMASK30 30 1 write-only GMASK31 GMASK31 31 1 write-only GMASK4 GMASK4 4 1 write-only GMASK5 GMASK5 5 1 write-only GMASK6 GMASK6 6 1 write-only GMASK7 GMASK7 7 1 write-only GMASK8 GMASK8 8 1 write-only GMASK9 GMASK9 9 1 write-only GCFG1 0xDC -1 read-write n GCFGMASK GLOBAL CONFIGUE MASK REGISTER 0xD0 32 read-write n 0xFFFFFFFF 0x0 GMASK0 GMASK0 0 1 read-write GMASK1 GMASK1 1 1 read-write GMASK10 GMASK10 10 1 read-write GMASK11 GMASK11 11 1 read-write GMASK12 GMASK12 12 1 read-write GMASK13 GMASK13 13 1 read-write GMASK14 GMASK14 14 1 read-write GMASK15 GMASK15 15 1 read-write GMASK16 GMASK16 16 1 read-write GMASK17 GMASK17 17 1 read-write GMASK18 GMASK18 18 1 read-write GMASK19 GMASK19 19 1 read-write GMASK2 GMASK2 2 1 read-write GMASK20 GMASK20 20 1 read-write GMASK21 GMASK21 21 1 read-write GMASK22 GMASK22 22 1 read-write GMASK23 GMASK23 23 1 read-write GMASK24 GMASK24 24 1 read-write GMASK25 GMASK25 25 1 read-write GMASK26 GMASK26 26 1 read-write GMASK27 GMASK27 27 1 read-write GMASK28 GMASK28 28 1 read-write GMASK29 GMASK29 29 1 read-write GMASK3 GMASK3 3 1 read-write GMASK30 GMASK30 30 1 read-write GMASK31 GMASK31 31 1 read-write GMASK4 GMASK4 4 1 read-write GMASK5 GMASK5 5 1 read-write GMASK6 GMASK6 6 1 read-write GMASK7 GMASK7 7 1 read-write GMASK8 GMASK8 8 1 read-write GMASK9 GMASK9 9 1 read-write INTBV Interrupt Double Edge Register 0xB8 32 read-write n 0x0 0xFFFFFFFF INTMASK Interrupt Mask Register 0xB0 32 read-write n 0xFFFFFFFF 0xFFFFFFFF INTPOL Interrupt Polarity Register 0xBC 32 read-write n 0x0 0xFFFFFFFF INTTYPE Interrupt Type Register 0xB4 32 read-write n 0x0 0xFFFFFFFF LOCK0 Configure LOCK Register 0 0xE0 32 read-write n 0x0 0xFFFFFFFF LOCKL0 LOCKL0 0 1 read-write LOCKL1 LOCKL1 1 1 read-write LOCKL10 LOCKL10 10 1 read-write LOCKL11 LOCKL11 11 1 read-write LOCKL12 LOCKL12 12 1 read-write LOCKL13 LOCKL13 13 1 read-write LOCKL14 LOCKL14 14 1 read-write LOCKL15 LOCKL15 15 1 read-write LOCKL2 LOCKL2 2 1 read-write LOCKL3 LOCKL3 3 1 read-write LOCKL4 LOCKL4 4 1 read-write LOCKL5 LOCKL5 5 1 read-write LOCKL6 LOCKL6 6 1 read-write LOCKL7 LOCKL7 7 1 read-write LOCKL8 LOCKL8 8 1 read-write LOCKL9 LOCKL9 9 1 read-write LOCKL_KEY LOCKL_KEY 16 16 read-write LOCK1 0xE4 -1 read-write n MIS Mask Interrupt Status Register 0xC4 32 read-write n 0x0 0xFFFFFFFF OUT Pin Output Register 0x90 32 read-write n 0x0 0xFFFFFFFF OUTCLR Pin Output Clear Register 0x98 32 read-write n 0x0 0xFFFFFFFF OUTEN Pin Output Enable Register 0xA0 32 read-write n 0x0 0xFFFFFFFF OUTSET Pin Output Set Register 0x94 32 read-write n 0x0 0xFFFFFFFF OUTTGL Pin Output Turn Register 0x9C 32 read-write n 0x0 0xFFFFFFFF PIN Pin Value Register 0x80 32 read-write n 0x0 0xFFFFFFFF IN0 IN0 0 1 read-write IN1 IN1 1 1 read-write IN10 IN10 10 1 read-write IN11 IN11 11 1 read-write IN12 IN12 12 1 read-write IN13 IN13 13 1 read-write IN14 IN14 14 1 read-write IN15 IN15 15 1 read-write IN16 IN16 16 1 read-write IN17 IN17 17 1 read-write IN18 IN18 18 1 read-write IN19 IN19 19 1 read-write IN2 IN2 2 1 read-write IN20 IN20 20 1 read-write IN21 IN21 21 1 read-write IN22 IN22 22 1 read-write IN23 IN23 23 1 read-write IN24 IN24 24 1 read-write IN25 IN25 25 1 read-write IN26 IN26 26 1 read-write IN27 IN27 27 1 read-write IN28 IN28 28 1 read-write IN29 IN29 29 1 read-write IN3 IN3 3 1 read-write IN30 IN30 30 1 read-write IN31 IN31 31 1 read-write IN4 IN4 4 1 read-write IN5 IN5 5 1 read-write IN6 IN6 6 1 read-write IN7 IN7 7 1 read-write IN8 IN8 8 1 read-write IN9 IN9 9 1 read-write RIS Original Interrupt Status Register 0xC0 32 read-write n 0x0 0xFFFFFFFF VERSION GPIO VERSION 0xC00 32 read-only n 0xD6610 0xFFFFFFFF PB PA P0RT 0x40001000 0x0 0xC04 registers n PB PB Interrupt 17 CFG0 PORT Control Register 0x0 32 read-write n 0x0 0xFFFFFFFF ANAEN ANAEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG1 0x4 -1 read-write n CFG10 0x28 -1 read-write n CFG11 0x2C -1 read-write n CFG12 0x30 -1 read-write n CFG13 0x34 -1 read-write n CFG14 0x38 -1 read-write n CFG15 0x3C -1 read-write n CFG16 0x40 -1 read-write n CFG17 0x44 -1 read-write n CFG18 0x48 -1 read-write n CFG19 0x4C -1 read-write n CFG2 0x8 -1 read-write n CFG20 0x50 -1 read-write n CFG21 0x54 -1 read-write n CFG22 0x58 -1 read-write n CFG23 0x5C -1 read-write n CFG24 0x60 -1 read-write n CFG25 0x64 -1 read-write n CFG26 0x68 -1 read-write n CFG27 0x6C -1 read-write n CFG28 0x70 -1 read-write n CFG29 0x74 -1 read-write n CFG3 0xC -1 read-write n CFG30 0x78 -1 read-write n CFG31 0x7C -1 read-write n CFG4 0x10 -1 read-write n CFG5 0x14 -1 read-write n CFG6 0x18 -1 read-write n CFG7 0x1C -1 read-write n CFG8 0x20 -1 read-write n CFG9 0x24 -1 read-write n GCFG0 Global Configuration Register 0 0xD8 32 write-only n 0x0 0xFFFFFFFF GMASK0 GMASK0 0 1 write-only GMASK1 GMASK1 1 1 write-only GMASK10 GMASK10 10 1 write-only GMASK11 GMASK11 11 1 write-only GMASK12 GMASK12 12 1 write-only GMASK13 GMASK13 13 1 write-only GMASK14 GMASK14 14 1 write-only GMASK15 GMASK15 15 1 write-only GMASK16 GMASK16 16 1 write-only GMASK17 GMASK17 17 1 write-only GMASK18 GMASK18 18 1 write-only GMASK19 GMASK19 19 1 write-only GMASK2 GMASK2 2 1 write-only GMASK20 GMASK20 20 1 write-only GMASK21 GMASK21 21 1 write-only GMASK22 GMASK22 22 1 write-only GMASK23 GMASK23 23 1 write-only GMASK24 GMASK24 24 1 write-only GMASK25 GMASK25 25 1 write-only GMASK26 GMASK26 26 1 write-only GMASK27 GMASK27 27 1 write-only GMASK28 GMASK28 28 1 write-only GMASK29 GMASK29 29 1 write-only GMASK3 GMASK3 3 1 write-only GMASK30 GMASK30 30 1 write-only GMASK31 GMASK31 31 1 write-only GMASK4 GMASK4 4 1 write-only GMASK5 GMASK5 5 1 write-only GMASK6 GMASK6 6 1 write-only GMASK7 GMASK7 7 1 write-only GMASK8 GMASK8 8 1 write-only GMASK9 GMASK9 9 1 write-only GCFG1 0xDC -1 read-write n GCFGMASK GLOBAL CONFIGUE MASK REGISTER 0xD0 32 read-write n 0xFFFFFFFF 0x0 GMASK0 GMASK0 0 1 read-write GMASK1 GMASK1 1 1 read-write GMASK10 GMASK10 10 1 read-write GMASK11 GMASK11 11 1 read-write GMASK12 GMASK12 12 1 read-write GMASK13 GMASK13 13 1 read-write GMASK14 GMASK14 14 1 read-write GMASK15 GMASK15 15 1 read-write GMASK16 GMASK16 16 1 read-write GMASK17 GMASK17 17 1 read-write GMASK18 GMASK18 18 1 read-write GMASK19 GMASK19 19 1 read-write GMASK2 GMASK2 2 1 read-write GMASK20 GMASK20 20 1 read-write GMASK21 GMASK21 21 1 read-write GMASK22 GMASK22 22 1 read-write GMASK23 GMASK23 23 1 read-write GMASK24 GMASK24 24 1 read-write GMASK25 GMASK25 25 1 read-write GMASK26 GMASK26 26 1 read-write GMASK27 GMASK27 27 1 read-write GMASK28 GMASK28 28 1 read-write GMASK29 GMASK29 29 1 read-write GMASK3 GMASK3 3 1 read-write GMASK30 GMASK30 30 1 read-write GMASK31 GMASK31 31 1 read-write GMASK4 GMASK4 4 1 read-write GMASK5 GMASK5 5 1 read-write GMASK6 GMASK6 6 1 read-write GMASK7 GMASK7 7 1 read-write GMASK8 GMASK8 8 1 read-write GMASK9 GMASK9 9 1 read-write INTBV Interrupt Double Edge Register 0xB8 32 read-write n 0x0 0xFFFFFFFF INTMASK Interrupt Mask Register 0xB0 32 read-write n 0xFFFFFFFF 0xFFFFFFFF INTPOL Interrupt Polarity Register 0xBC 32 read-write n 0x0 0xFFFFFFFF INTTYPE Interrupt Type Register 0xB4 32 read-write n 0x0 0xFFFFFFFF LOCK0 Configure LOCK Register 0 0xE0 32 read-write n 0x0 0xFFFFFFFF LOCKL0 LOCKL0 0 1 read-write LOCKL1 LOCKL1 1 1 read-write LOCKL10 LOCKL10 10 1 read-write LOCKL11 LOCKL11 11 1 read-write LOCKL12 LOCKL12 12 1 read-write LOCKL13 LOCKL13 13 1 read-write LOCKL14 LOCKL14 14 1 read-write LOCKL15 LOCKL15 15 1 read-write LOCKL2 LOCKL2 2 1 read-write LOCKL3 LOCKL3 3 1 read-write LOCKL4 LOCKL4 4 1 read-write LOCKL5 LOCKL5 5 1 read-write LOCKL6 LOCKL6 6 1 read-write LOCKL7 LOCKL7 7 1 read-write LOCKL8 LOCKL8 8 1 read-write LOCKL9 LOCKL9 9 1 read-write LOCKL_KEY LOCKL_KEY 16 16 read-write LOCK1 0xE4 -1 read-write n MIS Mask Interrupt Status Register 0xC4 32 read-write n 0x0 0xFFFFFFFF OUT Pin Output Register 0x90 32 read-write n 0x0 0xFFFFFFFF OUTCLR Pin Output Clear Register 0x98 32 read-write n 0x0 0xFFFFFFFF OUTEN Pin Output Enable Register 0xA0 32 read-write n 0x0 0xFFFFFFFF OUTSET Pin Output Set Register 0x94 32 read-write n 0x0 0xFFFFFFFF OUTTGL Pin Output Turn Register 0x9C 32 read-write n 0x0 0xFFFFFFFF PIN Pin Value Register 0x80 32 read-write n 0x0 0xFFFFFFFF IN0 IN0 0 1 read-write IN1 IN1 1 1 read-write IN10 IN10 10 1 read-write IN11 IN11 11 1 read-write IN12 IN12 12 1 read-write IN13 IN13 13 1 read-write IN14 IN14 14 1 read-write IN15 IN15 15 1 read-write IN16 IN16 16 1 read-write IN17 IN17 17 1 read-write IN18 IN18 18 1 read-write IN19 IN19 19 1 read-write IN2 IN2 2 1 read-write IN20 IN20 20 1 read-write IN21 IN21 21 1 read-write IN22 IN22 22 1 read-write IN23 IN23 23 1 read-write IN24 IN24 24 1 read-write IN25 IN25 25 1 read-write IN26 IN26 26 1 read-write IN27 IN27 27 1 read-write IN28 IN28 28 1 read-write IN29 IN29 29 1 read-write IN3 IN3 3 1 read-write IN30 IN30 30 1 read-write IN31 IN31 31 1 read-write IN4 IN4 4 1 read-write IN5 IN5 5 1 read-write IN6 IN6 6 1 read-write IN7 IN7 7 1 read-write IN8 IN8 8 1 read-write IN9 IN9 9 1 read-write RIS Original Interrupt Status Register 0xC0 32 read-write n 0x0 0xFFFFFFFF VERSION GPIO VERSION 0xC00 32 read-only n 0xD6610 0xFFFFFFFF PC PA P0RT 0x40002000 0x0 0xC04 registers n PC PC Interrupt 18 CFG0 PORT Control Register 0x0 32 read-write n 0x0 0xFFFFFFFF ANAEN ANAEN 4 1 read-write CLKDIV CLKDIV 24 3 read-write DRV DRV 10 1 read-write FILT FILT 16 2 read-write FUNC FUNC 0 3 read-write INV INV 15 1 read-write OD OD 13 1 read-write PUPD PUPD 6 2 read-write SR SR 8 2 read-write CFG1 0x4 -1 read-write n CFG10 0x28 -1 read-write n CFG11 0x2C -1 read-write n CFG12 0x30 -1 read-write n CFG13 0x34 -1 read-write n CFG14 0x38 -1 read-write n CFG15 0x3C -1 read-write n CFG16 0x40 -1 read-write n CFG17 0x44 -1 read-write n CFG18 0x48 -1 read-write n CFG19 0x4C -1 read-write n CFG2 0x8 -1 read-write n CFG20 0x50 -1 read-write n CFG21 0x54 -1 read-write n CFG22 0x58 -1 read-write n CFG23 0x5C -1 read-write n CFG24 0x60 -1 read-write n CFG25 0x64 -1 read-write n CFG26 0x68 -1 read-write n CFG27 0x6C -1 read-write n CFG28 0x70 -1 read-write n CFG29 0x74 -1 read-write n CFG3 0xC -1 read-write n CFG30 0x78 -1 read-write n CFG31 0x7C -1 read-write n CFG4 0x10 -1 read-write n CFG5 0x14 -1 read-write n CFG6 0x18 -1 read-write n CFG7 0x1C -1 read-write n CFG8 0x20 -1 read-write n CFG9 0x24 -1 read-write n GCFG0 Global Configuration Register 0 0xD8 32 write-only n 0x0 0xFFFFFFFF GMASK0 GMASK0 0 1 write-only GMASK1 GMASK1 1 1 write-only GMASK10 GMASK10 10 1 write-only GMASK11 GMASK11 11 1 write-only GMASK12 GMASK12 12 1 write-only GMASK13 GMASK13 13 1 write-only GMASK14 GMASK14 14 1 write-only GMASK15 GMASK15 15 1 write-only GMASK16 GMASK16 16 1 write-only GMASK17 GMASK17 17 1 write-only GMASK18 GMASK18 18 1 write-only GMASK19 GMASK19 19 1 write-only GMASK2 GMASK2 2 1 write-only GMASK20 GMASK20 20 1 write-only GMASK21 GMASK21 21 1 write-only GMASK22 GMASK22 22 1 write-only GMASK23 GMASK23 23 1 write-only GMASK24 GMASK24 24 1 write-only GMASK25 GMASK25 25 1 write-only GMASK26 GMASK26 26 1 write-only GMASK27 GMASK27 27 1 write-only GMASK28 GMASK28 28 1 write-only GMASK29 GMASK29 29 1 write-only GMASK3 GMASK3 3 1 write-only GMASK30 GMASK30 30 1 write-only GMASK31 GMASK31 31 1 write-only GMASK4 GMASK4 4 1 write-only GMASK5 GMASK5 5 1 write-only GMASK6 GMASK6 6 1 write-only GMASK7 GMASK7 7 1 write-only GMASK8 GMASK8 8 1 write-only GMASK9 GMASK9 9 1 write-only GCFG1 0xDC -1 read-write n GCFGMASK GLOBAL CONFIGUE MASK REGISTER 0xD0 32 read-write n 0xFFFFFFFF 0x0 GMASK0 GMASK0 0 1 read-write GMASK1 GMASK1 1 1 read-write GMASK10 GMASK10 10 1 read-write GMASK11 GMASK11 11 1 read-write GMASK12 GMASK12 12 1 read-write GMASK13 GMASK13 13 1 read-write GMASK14 GMASK14 14 1 read-write GMASK15 GMASK15 15 1 read-write GMASK16 GMASK16 16 1 read-write GMASK17 GMASK17 17 1 read-write GMASK18 GMASK18 18 1 read-write GMASK19 GMASK19 19 1 read-write GMASK2 GMASK2 2 1 read-write GMASK20 GMASK20 20 1 read-write GMASK21 GMASK21 21 1 read-write GMASK22 GMASK22 22 1 read-write GMASK23 GMASK23 23 1 read-write GMASK24 GMASK24 24 1 read-write GMASK25 GMASK25 25 1 read-write GMASK26 GMASK26 26 1 read-write GMASK27 GMASK27 27 1 read-write GMASK28 GMASK28 28 1 read-write GMASK29 GMASK29 29 1 read-write GMASK3 GMASK3 3 1 read-write GMASK30 GMASK30 30 1 read-write GMASK31 GMASK31 31 1 read-write GMASK4 GMASK4 4 1 read-write GMASK5 GMASK5 5 1 read-write GMASK6 GMASK6 6 1 read-write GMASK7 GMASK7 7 1 read-write GMASK8 GMASK8 8 1 read-write GMASK9 GMASK9 9 1 read-write INTBV Interrupt Double Edge Register 0xB8 32 read-write n 0x0 0xFFFFFFFF INTMASK Interrupt Mask Register 0xB0 32 read-write n 0xFFFFFFFF 0xFFFFFFFF INTPOL Interrupt Polarity Register 0xBC 32 read-write n 0x0 0xFFFFFFFF INTTYPE Interrupt Type Register 0xB4 32 read-write n 0x0 0xFFFFFFFF LOCK0 Configure LOCK Register 0 0xE0 32 read-write n 0x0 0xFFFFFFFF LOCKL0 LOCKL0 0 1 read-write LOCKL1 LOCKL1 1 1 read-write LOCKL10 LOCKL10 10 1 read-write LOCKL11 LOCKL11 11 1 read-write LOCKL12 LOCKL12 12 1 read-write LOCKL13 LOCKL13 13 1 read-write LOCKL14 LOCKL14 14 1 read-write LOCKL15 LOCKL15 15 1 read-write LOCKL2 LOCKL2 2 1 read-write LOCKL3 LOCKL3 3 1 read-write LOCKL4 LOCKL4 4 1 read-write LOCKL5 LOCKL5 5 1 read-write LOCKL6 LOCKL6 6 1 read-write LOCKL7 LOCKL7 7 1 read-write LOCKL8 LOCKL8 8 1 read-write LOCKL9 LOCKL9 9 1 read-write LOCKL_KEY LOCKL_KEY 16 16 read-write LOCK1 0xE4 -1 read-write n MIS Mask Interrupt Status Register 0xC4 32 read-write n 0x0 0xFFFFFFFF OUT Pin Output Register 0x90 32 read-write n 0x0 0xFFFFFFFF OUTCLR Pin Output Clear Register 0x98 32 read-write n 0x0 0xFFFFFFFF OUTEN Pin Output Enable Register 0xA0 32 read-write n 0x0 0xFFFFFFFF OUTSET Pin Output Set Register 0x94 32 read-write n 0x0 0xFFFFFFFF OUTTGL Pin Output Turn Register 0x9C 32 read-write n 0x0 0xFFFFFFFF PIN Pin Value Register 0x80 32 read-write n 0x0 0xFFFFFFFF IN0 IN0 0 1 read-write IN1 IN1 1 1 read-write IN10 IN10 10 1 read-write IN11 IN11 11 1 read-write IN12 IN12 12 1 read-write IN13 IN13 13 1 read-write IN14 IN14 14 1 read-write IN15 IN15 15 1 read-write IN16 IN16 16 1 read-write IN17 IN17 17 1 read-write IN18 IN18 18 1 read-write IN19 IN19 19 1 read-write IN2 IN2 2 1 read-write IN20 IN20 20 1 read-write IN21 IN21 21 1 read-write IN22 IN22 22 1 read-write IN23 IN23 23 1 read-write IN24 IN24 24 1 read-write IN25 IN25 25 1 read-write IN26 IN26 26 1 read-write IN27 IN27 27 1 read-write IN28 IN28 28 1 read-write IN29 IN29 29 1 read-write IN3 IN3 3 1 read-write IN30 IN30 30 1 read-write IN31 IN31 31 1 read-write IN4 IN4 4 1 read-write IN5 IN5 5 1 read-write IN6 IN6 6 1 read-write IN7 IN7 7 1 read-write IN8 IN8 8 1 read-write IN9 IN9 9 1 read-write RIS Original Interrupt Status Register 0xC0 32 read-write n 0x0 0xFFFFFFFF VERSION GPIO VERSION 0xC00 32 read-only n 0xD6610 0xFFFFFFFF PPU PPU PPU 0x40082000 0x0 0x80 registers n CTRL CTRL Register 0x0 32 read-write n 0x0 0xFFFFFFFF ppu_hps01_intr_en ppu_hps01_intr_en 8 1 read-write ppu_hps23_intr_en ppu_hps23_intr_en 9 1 read-write ppu_pps01_intr_en ppu_pps01_intr_en 12 1 read-write ppu_pps23_intr_en ppu_pps23_intr_en 13 1 read-write ppu_ram_intr_en ppu_ram_intr_en 4 1 read-write HPS01_PROT HPS01_PROT Register 0x20 32 read-write n 0xFFFF 0xFFFFFFFF PA_en PA_en 0 1 read-write PB_en PB_en 1 1 read-write PC_en PC_en 3 1 read-write HPS01_TRAP HPS01_TRAP Register 0x60 32 read-write n 0xFFFF 0xFFFFFFFF PA_en PA_en 0 1 read-write PB_en PB_en 1 1 read-write PC_en PC_en 2 1 read-write HPS23_PROT HPS23_PROT Register 0x24 32 read-write n 0xFFFF 0xFFFFFFFF coproc_en coproc_en 0 1 read-write HPS23_TRAP HPS23_TRAP Register 0x64 32 read-write n 0xFFFF 0xFFFFFFFF coproc_en coproc_en 0 1 read-write PPS01_PROT PPS01_PROT Register 0x30 32 read-write n 0xFFFF 0xFFFFFFFF chipctrl_en chipctrl_en 1 1 read-write dma_en dma_en 6 1 read-write eflash_en eflash_en 8 1 read-write eru_en eru_en 3 1 read-write i2c_en i2c_en 23 1 read-write ssp_en ssp_en 24 1 read-write syscfg_en syscfg_en 0 1 read-write uart0_en uart0_en 16 1 read-write uart1_en uart1_en 17 1 read-write uart2_en uart2_en 18 1 read-write WDT_en WDT_en 12 1 read-write PPS01_TRAP PPS01_TRAP Register 0x70 32 read-write n 0xFFFF 0xFFFFFFFF chipctrl_en chipctrl_en 1 1 read-write dma_en dma_en 6 1 read-write eflash_en eflash_en 8 1 read-write eru_en eru_en 3 1 read-write i2c_en i2c_en 23 1 read-write ssp_en ssp_en 24 1 read-write syscfg_en syscfg_en 0 1 read-write uart0_en uart0_en 16 1 read-write uart1_en uart1_en 17 1 read-write uart2_en uart2_en 18 1 read-write WDT_en WDT_en 12 1 read-write PPS23_PROT PPS23_PROT Register 0x34 32 read-write n 0xFFFFFFFF 0xFFFFFFFF acmp_opa_en acmp_opa_en 10 1 read-write adc_en adc_en 8 1 read-write pwmtop0_en pwmtop0_en 4 1 read-write pwmtop1_en pwmtop1_en 5 1 read-write Timertop0_en Timertop0_en 12 1 read-write Timertop1_en Timertop1_en 13 1 read-write Timertop6_en Timertop6_en 15 1 read-write PPS23_TRAP PPS23_PROT Register 0x74 32 read-write n 0xFFFFFFFF 0xFFFFFFFF acmp_opa_en acmp_opa_en 10 1 read-write adc_en adc_en 8 1 read-write pwmtop0_en pwmtop0_en 4 1 read-write pwmtop1_en pwmtop1_en 5 1 read-write Timertop0_en Timertop0_en 12 1 read-write Timertop1_en Timertop1_en 13 1 read-write Timertop6_en Timertop6_en 15 1 read-write RAM_PROT RAM_PROT Register 0x10 32 read-write n 0xFFFFFFFF 0xFFFFFFFF RAM_TRAP RAM_TRAP Register 0x50 32 read-write n 0xFFFF 0xFFFFFFFF PWM0 PWM0 PWM 0x400A4000 0x0 0xB8 registers n PWM0 PWM0 Interrupt 23 PWM PWM_COMB Interrupt 27 AQCSFRC Action Qualify Software Continuous Force Register 0x38 32 read-write n 0x0 0xFFFFFFFF CSFA A0 Event Source Select 0 2 read-write CSFB B0 Event Source Select 2 2 read-write AQCTLA Action Qualify output channel A control register 0x2C 32 read-write n 0x0 0xFFFFFFFF CAD B1 Event Source Select 6 2 read-write CAU A1 Event Source Select 4 2 read-write CBD B2 Event Source Select 10 2 read-write CBU A2 Event Source Select 8 2 read-write PRU B0 Event Source Select 2 2 read-write ZRO A0 Event Source Select 0 2 read-write AQCTLB Action Qualify Output Channel A Control Register 0x30 32 read-write n 0x0 0xFFFFFFFF CAD B1 Event Source Select 6 2 read-write CAU A1 Event Source Select 4 2 read-write CBD B2 Event Source Select 10 2 read-write CBU A2 Event Source Select 8 2 read-write PRU B0 Event Source Select 2 2 read-write ZRO A0 Event Source Select 0 2 read-write AQSFRC Action Qualify Software Force Register 0x34 32 read-write n 0x0 0xFFFFFFFF ACTSFA A0 Event Source Select 0 2 read-write ACTSFB A1 Event Source Select 3 2 read-write BLDCSF A2 Event Source Select 6 2 read-write OTSFA B0 Event Source Select 2 1 read-write OTSFB B1 Event Source Select 5 1 read-write CMPA Comparison function Register A 0x24 32 read-write n 0x0 0xFFFFFFFF CMPAM Compare Register A Mirror 0xB4 32 read-write n 0x0 0xFFFFFFFF CMPB Comparison function Register B 0x28 32 read-write n 0x0 0xFFFFFFFF CMPCTL Comparison function control register 0x1C 32 read-write n 0x0 0xFFFFFFFF LOADAMODE A0 Event Source Select 0 2 read-write LOADBMODE B0 Event Source Select 2 2 read-write SHDWAFULL A2 Event Source Select 8 1 read-only SHDWAMODE A1 Event Source Select 4 1 read-write SHDWBFULL B2 Event Source Select 9 1 read-only SHDWBMODE B1 Event Source Select 6 1 read-write DBCTL Dead Zone Control Register 0x3C 32 read-write n 0x0 0xFFFFFFFF HALFCYCLE B0 Event Source Select 15 1 read-write IN_MODE A0 Event Source Select 4 2 read-write OUT_MODE A0 Event Source Select 0 2 read-write POLSEL B0 Event Source Select 2 2 read-write DBFED Falling Edge Dead Zorn Delay Setting Register 0x44 32 read-write n 0x0 0xFFFFFFFF DBRED Rising Edge Dead Zorn Delay Setting Register 0x40 32 read-write n 0x0 0xFFFFFFFF ETCLR Event trigger clear 0x70 32 read-write n 0x0 0xFFFFFFFF INT A0 Event Source Select 0 1 read-write SOCA B0 Event Source Select 2 1 read-write SOCB A0 Event Source Select 3 1 read-write ETFLG Event trigger flags 0x6C 32 read-write n 0x0 0xFFFFFFFF CTRDIR B0 Event Source Select 31 1 read-only INT A0 Event Source Select 0 1 read-only SOCA B0 Event Source Select 2 1 read-only SOCB A0 Event Source Select 3 1 read-only ETFRC Event trigger force 0x74 32 read-write n 0x0 0xFFFFFFFF INT A0 Event Source Select 0 1 read-write SOCA B0 Event Source Select 2 1 read-write SOCB A0 Event Source Select 3 1 read-write ETPS Event trigger pre-scaler 0x68 32 read-write n 0x0 0xFFFFFFFF INTCNT B0 Event Source Select 2 2 read-only INTPRD A0 Event Source Select 0 2 read-write SOCACNT B0 Event Source Select 10 2 read-only SOCAPRD A0 Event Source Select 8 2 read-write SOCBCNT B0 Event Source Select 14 2 read-only SOCBPRD A0 Event Source Select 12 2 read-write ETSEL Event trigger selection 0x64 32 read-write n 0x0 0xFFFFFFFF INTEN B0 Event Source Select 3 1 read-write INTESEL A0 Event Source Select 0 3 read-write SOCAEN B0 Event Source Select 11 1 read-write SOCASEL A0 Event Source Select 8 3 read-write SOCBEN B0 Event Source Select 15 1 read-write SOCBSEL A0 Event Source Select 12 3 read-write TBCTL Time Reference Control Register 0x0 32 read-write n 0x0 0xFFFFFFFF CLKDIV A3 Event Source Select 10 3 read-write CTRMODE Time Reference Status Register 0 2 read-write FREE_SOFT B3 Event Source Select 14 2 read-write HSPCLKDIV B2 Event Source Select 7 3 read-write PHSDIR B3 Event Source Select 13 1 read-write PHSEN Time Reference Phase Register 2 1 read-write PRDLD Time Reference Counter Register 3 1 read-write SWFSYNC A2 Event Source Select 6 1 read-write SYNCOSEL B1 Event Source Select 4 2 read-write TBCTR Time Reference Counter Register 0x10 32 read-write n 0x0 0xFFFFFFFF TBPHS Time Reference Phase Register 0xC 32 read-write n 0x0 0xFFFFFFFF TBPRD Time Reference Period Register 0x14 32 read-write n 0x0 0xFFFFFFFF TBPRDM Time Base Period register Mirror 0xAC 32 read-write n 0x0 0xFFFFFFFF TBSTS Time Reference Status Register 0x4 32 read-write n 0x1 0xFFFFFFFF CTRDIR A0 Event Source Select 0 1 read-write CTRMAX A1 Event Source Select 2 1 read-write SYNCI B0 Event Source Select 1 1 read-write TZCLR Trip zone clear 0x5C 32 read-write n 0x0 0xFFFFFFFF CBC A0 Event Source Select 1 1 read-write INT A0 Event Source Select 0 1 read-write OST B0 Event Source Select 2 1 read-write TZCTL Trip zone control 0x50 32 read-write n 0x0 0xFFFFFFFF SYNC_OUTEN A0 Event Source Select 31 1 read-write TZA A0 Event Source Select 0 2 read-write TZB B0 Event Source Select 2 2 read-write TZEINT Trip zone interrupt enable 0x54 32 read-write n 0x0 0xFFFFFFFF CBC A0 Event Source Select 1 1 read-write OST B0 Event Source Select 2 1 read-write TZFLG Trip zone interrupt flags 0x58 32 read-only n 0x0 0xFFFFFFFF CBC A0 Event Source Select 1 1 read-only INT A0 Event Source Select 0 1 read-only OST B0 Event Source Select 2 1 read-only TZFRC Trip zone force interrupt 0x60 32 read-write n 0x0 0xFFFFFFFF CBC A0 Event Source Select 1 1 read-write OST B0 Event Source Select 2 1 read-write TZSEL Trip zone select 0x48 32 read-write n 0x0 0xFFFFFFFF CBC0 A0 Event Source Select 0 1 read-write CBC1 B0 Event Source Select 1 1 read-write CBC2 A0 Event Source Select 2 1 read-write CBC3 B0 Event Source Select 3 1 read-write CBC4 A0 Event Source Select 4 1 read-write CBC5 B0 Event Source Select 5 1 read-write OSHT0 A0 Event Source Select 8 1 read-write OSHT1 B0 Event Source Select 9 1 read-write OSHT2 A0 Event Source Select 10 1 read-write OSHT3 B0 Event Source Select 11 1 read-write OSHT4 A0 Event Source Select 12 1 read-write OSHT5 B0 Event Source Select 13 1 read-write PWM1 PWM0 PWM 0x400A4400 0x0 0xB8 registers n PWM0 PWM0 Interrupt 23 PWM PWM_COMB Interrupt 27 AQCSFRC Action Qualify Software Continuous Force Register 0x38 32 read-write n 0x0 0xFFFFFFFF CSFA A0 Event Source Select 0 2 read-write CSFB B0 Event Source Select 2 2 read-write AQCTLA Action Qualify output channel A control register 0x2C 32 read-write n 0x0 0xFFFFFFFF CAD B1 Event Source Select 6 2 read-write CAU A1 Event Source Select 4 2 read-write CBD B2 Event Source Select 10 2 read-write CBU A2 Event Source Select 8 2 read-write PRU B0 Event Source Select 2 2 read-write ZRO A0 Event Source Select 0 2 read-write AQCTLB Action Qualify Output Channel A Control Register 0x30 32 read-write n 0x0 0xFFFFFFFF CAD B1 Event Source Select 6 2 read-write CAU A1 Event Source Select 4 2 read-write CBD B2 Event Source Select 10 2 read-write CBU A2 Event Source Select 8 2 read-write PRU B0 Event Source Select 2 2 read-write ZRO A0 Event Source Select 0 2 read-write AQSFRC Action Qualify Software Force Register 0x34 32 read-write n 0x0 0xFFFFFFFF ACTSFA A0 Event Source Select 0 2 read-write ACTSFB A1 Event Source Select 3 2 read-write BLDCSF A2 Event Source Select 6 2 read-write OTSFA B0 Event Source Select 2 1 read-write OTSFB B1 Event Source Select 5 1 read-write CMPA Comparison function Register A 0x24 32 read-write n 0x0 0xFFFFFFFF CMPAM Compare Register A Mirror 0xB4 32 read-write n 0x0 0xFFFFFFFF CMPB Comparison function Register B 0x28 32 read-write n 0x0 0xFFFFFFFF CMPCTL Comparison function control register 0x1C 32 read-write n 0x0 0xFFFFFFFF LOADAMODE A0 Event Source Select 0 2 read-write LOADBMODE B0 Event Source Select 2 2 read-write SHDWAFULL A2 Event Source Select 8 1 read-only SHDWAMODE A1 Event Source Select 4 1 read-write SHDWBFULL B2 Event Source Select 9 1 read-only SHDWBMODE B1 Event Source Select 6 1 read-write DBCTL Dead Zone Control Register 0x3C 32 read-write n 0x0 0xFFFFFFFF HALFCYCLE B0 Event Source Select 15 1 read-write IN_MODE A0 Event Source Select 4 2 read-write OUT_MODE A0 Event Source Select 0 2 read-write POLSEL B0 Event Source Select 2 2 read-write DBFED Falling Edge Dead Zorn Delay Setting Register 0x44 32 read-write n 0x0 0xFFFFFFFF DBRED Rising Edge Dead Zorn Delay Setting Register 0x40 32 read-write n 0x0 0xFFFFFFFF ETCLR Event trigger clear 0x70 32 read-write n 0x0 0xFFFFFFFF INT A0 Event Source Select 0 1 read-write SOCA B0 Event Source Select 2 1 read-write SOCB A0 Event Source Select 3 1 read-write ETFLG Event trigger flags 0x6C 32 read-write n 0x0 0xFFFFFFFF CTRDIR B0 Event Source Select 31 1 read-only INT A0 Event Source Select 0 1 read-only SOCA B0 Event Source Select 2 1 read-only SOCB A0 Event Source Select 3 1 read-only ETFRC Event trigger force 0x74 32 read-write n 0x0 0xFFFFFFFF INT A0 Event Source Select 0 1 read-write SOCA B0 Event Source Select 2 1 read-write SOCB A0 Event Source Select 3 1 read-write ETPS Event trigger pre-scaler 0x68 32 read-write n 0x0 0xFFFFFFFF INTCNT B0 Event Source Select 2 2 read-only INTPRD A0 Event Source Select 0 2 read-write SOCACNT B0 Event Source Select 10 2 read-only SOCAPRD A0 Event Source Select 8 2 read-write SOCBCNT B0 Event Source Select 14 2 read-only SOCBPRD A0 Event Source Select 12 2 read-write ETSEL Event trigger selection 0x64 32 read-write n 0x0 0xFFFFFFFF INTEN B0 Event Source Select 3 1 read-write INTESEL A0 Event Source Select 0 3 read-write SOCAEN B0 Event Source Select 11 1 read-write SOCASEL A0 Event Source Select 8 3 read-write SOCBEN B0 Event Source Select 15 1 read-write SOCBSEL A0 Event Source Select 12 3 read-write TBCTL Time Reference Control Register 0x0 32 read-write n 0x0 0xFFFFFFFF CLKDIV A3 Event Source Select 10 3 read-write CTRMODE Time Reference Status Register 0 2 read-write FREE_SOFT B3 Event Source Select 14 2 read-write HSPCLKDIV B2 Event Source Select 7 3 read-write PHSDIR B3 Event Source Select 13 1 read-write PHSEN Time Reference Phase Register 2 1 read-write PRDLD Time Reference Counter Register 3 1 read-write SWFSYNC A2 Event Source Select 6 1 read-write SYNCOSEL B1 Event Source Select 4 2 read-write TBCTR Time Reference Counter Register 0x10 32 read-write n 0x0 0xFFFFFFFF TBPHS Time Reference Phase Register 0xC 32 read-write n 0x0 0xFFFFFFFF TBPRD Time Reference Period Register 0x14 32 read-write n 0x0 0xFFFFFFFF TBPRDM Time Base Period register Mirror 0xAC 32 read-write n 0x0 0xFFFFFFFF TBSTS Time Reference Status Register 0x4 32 read-write n 0x1 0xFFFFFFFF CTRDIR A0 Event Source Select 0 1 read-write CTRMAX A1 Event Source Select 2 1 read-write SYNCI B0 Event Source Select 1 1 read-write TZCLR Trip zone clear 0x5C 32 read-write n 0x0 0xFFFFFFFF CBC A0 Event Source Select 1 1 read-write INT A0 Event Source Select 0 1 read-write OST B0 Event Source Select 2 1 read-write TZCTL Trip zone control 0x50 32 read-write n 0x0 0xFFFFFFFF SYNC_OUTEN A0 Event Source Select 31 1 read-write TZA A0 Event Source Select 0 2 read-write TZB B0 Event Source Select 2 2 read-write TZEINT Trip zone interrupt enable 0x54 32 read-write n 0x0 0xFFFFFFFF CBC A0 Event Source Select 1 1 read-write OST B0 Event Source Select 2 1 read-write TZFLG Trip zone interrupt flags 0x58 32 read-only n 0x0 0xFFFFFFFF CBC A0 Event Source Select 1 1 read-only INT A0 Event Source Select 0 1 read-only OST B0 Event Source Select 2 1 read-only TZFRC Trip zone force interrupt 0x60 32 read-write n 0x0 0xFFFFFFFF CBC A0 Event Source Select 1 1 read-write OST B0 Event Source Select 2 1 read-write TZSEL Trip zone select 0x48 32 read-write n 0x0 0xFFFFFFFF CBC0 A0 Event Source Select 0 1 read-write CBC1 B0 Event Source Select 1 1 read-write CBC2 A0 Event Source Select 2 1 read-write CBC3 B0 Event Source Select 3 1 read-write CBC4 A0 Event Source Select 4 1 read-write CBC5 B0 Event Source Select 5 1 read-write OSHT0 A0 Event Source Select 8 1 read-write OSHT1 B0 Event Source Select 9 1 read-write OSHT2 A0 Event Source Select 10 1 read-write OSHT3 B0 Event Source Select 11 1 read-write OSHT4 A0 Event Source Select 12 1 read-write OSHT5 B0 Event Source Select 13 1 read-write PWM2 PWM0 PWM 0x400A4800 0x0 0xB8 registers n PWM0 PWM0 Interrupt 23 PWM PWM_COMB Interrupt 27 AQCSFRC Action Qualify Software Continuous Force Register 0x38 32 read-write n 0x0 0xFFFFFFFF CSFA A0 Event Source Select 0 2 read-write CSFB B0 Event Source Select 2 2 read-write AQCTLA Action Qualify output channel A control register 0x2C 32 read-write n 0x0 0xFFFFFFFF CAD B1 Event Source Select 6 2 read-write CAU A1 Event Source Select 4 2 read-write CBD B2 Event Source Select 10 2 read-write CBU A2 Event Source Select 8 2 read-write PRU B0 Event Source Select 2 2 read-write ZRO A0 Event Source Select 0 2 read-write AQCTLB Action Qualify Output Channel A Control Register 0x30 32 read-write n 0x0 0xFFFFFFFF CAD B1 Event Source Select 6 2 read-write CAU A1 Event Source Select 4 2 read-write CBD B2 Event Source Select 10 2 read-write CBU A2 Event Source Select 8 2 read-write PRU B0 Event Source Select 2 2 read-write ZRO A0 Event Source Select 0 2 read-write AQSFRC Action Qualify Software Force Register 0x34 32 read-write n 0x0 0xFFFFFFFF ACTSFA A0 Event Source Select 0 2 read-write ACTSFB A1 Event Source Select 3 2 read-write BLDCSF A2 Event Source Select 6 2 read-write OTSFA B0 Event Source Select 2 1 read-write OTSFB B1 Event Source Select 5 1 read-write CMPA Comparison function Register A 0x24 32 read-write n 0x0 0xFFFFFFFF CMPAM Compare Register A Mirror 0xB4 32 read-write n 0x0 0xFFFFFFFF CMPB Comparison function Register B 0x28 32 read-write n 0x0 0xFFFFFFFF CMPCTL Comparison function control register 0x1C 32 read-write n 0x0 0xFFFFFFFF LOADAMODE A0 Event Source Select 0 2 read-write LOADBMODE B0 Event Source Select 2 2 read-write SHDWAFULL A2 Event Source Select 8 1 read-only SHDWAMODE A1 Event Source Select 4 1 read-write SHDWBFULL B2 Event Source Select 9 1 read-only SHDWBMODE B1 Event Source Select 6 1 read-write DBCTL Dead Zone Control Register 0x3C 32 read-write n 0x0 0xFFFFFFFF HALFCYCLE B0 Event Source Select 15 1 read-write IN_MODE A0 Event Source Select 4 2 read-write OUT_MODE A0 Event Source Select 0 2 read-write POLSEL B0 Event Source Select 2 2 read-write DBFED Falling Edge Dead Zorn Delay Setting Register 0x44 32 read-write n 0x0 0xFFFFFFFF DBRED Rising Edge Dead Zorn Delay Setting Register 0x40 32 read-write n 0x0 0xFFFFFFFF ETCLR Event trigger clear 0x70 32 read-write n 0x0 0xFFFFFFFF INT A0 Event Source Select 0 1 read-write SOCA B0 Event Source Select 2 1 read-write SOCB A0 Event Source Select 3 1 read-write ETFLG Event trigger flags 0x6C 32 read-write n 0x0 0xFFFFFFFF CTRDIR B0 Event Source Select 31 1 read-only INT A0 Event Source Select 0 1 read-only SOCA B0 Event Source Select 2 1 read-only SOCB A0 Event Source Select 3 1 read-only ETFRC Event trigger force 0x74 32 read-write n 0x0 0xFFFFFFFF INT A0 Event Source Select 0 1 read-write SOCA B0 Event Source Select 2 1 read-write SOCB A0 Event Source Select 3 1 read-write ETPS Event trigger pre-scaler 0x68 32 read-write n 0x0 0xFFFFFFFF INTCNT B0 Event Source Select 2 2 read-only INTPRD A0 Event Source Select 0 2 read-write SOCACNT B0 Event Source Select 10 2 read-only SOCAPRD A0 Event Source Select 8 2 read-write SOCBCNT B0 Event Source Select 14 2 read-only SOCBPRD A0 Event Source Select 12 2 read-write ETSEL Event trigger selection 0x64 32 read-write n 0x0 0xFFFFFFFF INTEN B0 Event Source Select 3 1 read-write INTESEL A0 Event Source Select 0 3 read-write SOCAEN B0 Event Source Select 11 1 read-write SOCASEL A0 Event Source Select 8 3 read-write SOCBEN B0 Event Source Select 15 1 read-write SOCBSEL A0 Event Source Select 12 3 read-write TBCTL Time Reference Control Register 0x0 32 read-write n 0x0 0xFFFFFFFF CLKDIV A3 Event Source Select 10 3 read-write CTRMODE Time Reference Status Register 0 2 read-write FREE_SOFT B3 Event Source Select 14 2 read-write HSPCLKDIV B2 Event Source Select 7 3 read-write PHSDIR B3 Event Source Select 13 1 read-write PHSEN Time Reference Phase Register 2 1 read-write PRDLD Time Reference Counter Register 3 1 read-write SWFSYNC A2 Event Source Select 6 1 read-write SYNCOSEL B1 Event Source Select 4 2 read-write TBCTR Time Reference Counter Register 0x10 32 read-write n 0x0 0xFFFFFFFF TBPHS Time Reference Phase Register 0xC 32 read-write n 0x0 0xFFFFFFFF TBPRD Time Reference Period Register 0x14 32 read-write n 0x0 0xFFFFFFFF TBPRDM Time Base Period register Mirror 0xAC 32 read-write n 0x0 0xFFFFFFFF TBSTS Time Reference Status Register 0x4 32 read-write n 0x1 0xFFFFFFFF CTRDIR A0 Event Source Select 0 1 read-write CTRMAX A1 Event Source Select 2 1 read-write SYNCI B0 Event Source Select 1 1 read-write TZCLR Trip zone clear 0x5C 32 read-write n 0x0 0xFFFFFFFF CBC A0 Event Source Select 1 1 read-write INT A0 Event Source Select 0 1 read-write OST B0 Event Source Select 2 1 read-write TZCTL Trip zone control 0x50 32 read-write n 0x0 0xFFFFFFFF SYNC_OUTEN A0 Event Source Select 31 1 read-write TZA A0 Event Source Select 0 2 read-write TZB B0 Event Source Select 2 2 read-write TZEINT Trip zone interrupt enable 0x54 32 read-write n 0x0 0xFFFFFFFF CBC A0 Event Source Select 1 1 read-write OST B0 Event Source Select 2 1 read-write TZFLG Trip zone interrupt flags 0x58 32 read-only n 0x0 0xFFFFFFFF CBC A0 Event Source Select 1 1 read-only INT A0 Event Source Select 0 1 read-only OST B0 Event Source Select 2 1 read-only TZFRC Trip zone force interrupt 0x60 32 read-write n 0x0 0xFFFFFFFF CBC A0 Event Source Select 1 1 read-write OST B0 Event Source Select 2 1 read-write TZSEL Trip zone select 0x48 32 read-write n 0x0 0xFFFFFFFF CBC0 A0 Event Source Select 0 1 read-write CBC1 B0 Event Source Select 1 1 read-write CBC2 A0 Event Source Select 2 1 read-write CBC3 B0 Event Source Select 3 1 read-write CBC4 A0 Event Source Select 4 1 read-write CBC5 B0 Event Source Select 5 1 read-write OSHT0 A0 Event Source Select 8 1 read-write OSHT1 B0 Event Source Select 9 1 read-write OSHT2 A0 Event Source Select 10 1 read-write OSHT3 B0 Event Source Select 11 1 read-write OSHT4 A0 Event Source Select 12 1 read-write OSHT5 B0 Event Source Select 13 1 read-write PWM4 PWM0 PWM 0x400A5000 0x0 0xB8 registers n PWM4 PWM4 Interrupt 25 AQCSFRC Action Qualify Software Continuous Force Register 0x38 32 read-write n 0x0 0xFFFFFFFF CSFA A0 Event Source Select 0 2 read-write CSFB B0 Event Source Select 2 2 read-write AQCTLA Action Qualify output channel A control register 0x2C 32 read-write n 0x0 0xFFFFFFFF CAD B1 Event Source Select 6 2 read-write CAU A1 Event Source Select 4 2 read-write CBD B2 Event Source Select 10 2 read-write CBU A2 Event Source Select 8 2 read-write PRU B0 Event Source Select 2 2 read-write ZRO A0 Event Source Select 0 2 read-write AQCTLB Action Qualify Output Channel A Control Register 0x30 32 read-write n 0x0 0xFFFFFFFF CAD B1 Event Source Select 6 2 read-write CAU A1 Event Source Select 4 2 read-write CBD B2 Event Source Select 10 2 read-write CBU A2 Event Source Select 8 2 read-write PRU B0 Event Source Select 2 2 read-write ZRO A0 Event Source Select 0 2 read-write AQSFRC Action Qualify Software Force Register 0x34 32 read-write n 0x0 0xFFFFFFFF ACTSFA A0 Event Source Select 0 2 read-write ACTSFB A1 Event Source Select 3 2 read-write BLDCSF A2 Event Source Select 6 2 read-write OTSFA B0 Event Source Select 2 1 read-write OTSFB B1 Event Source Select 5 1 read-write CMPA Comparison function Register A 0x24 32 read-write n 0x0 0xFFFFFFFF CMPAM Compare Register A Mirror 0xB4 32 read-write n 0x0 0xFFFFFFFF CMPB Comparison function Register B 0x28 32 read-write n 0x0 0xFFFFFFFF CMPCTL Comparison function control register 0x1C 32 read-write n 0x0 0xFFFFFFFF LOADAMODE A0 Event Source Select 0 2 read-write LOADBMODE B0 Event Source Select 2 2 read-write SHDWAFULL A2 Event Source Select 8 1 read-only SHDWAMODE A1 Event Source Select 4 1 read-write SHDWBFULL B2 Event Source Select 9 1 read-only SHDWBMODE B1 Event Source Select 6 1 read-write DBCTL Dead Zone Control Register 0x3C 32 read-write n 0x0 0xFFFFFFFF HALFCYCLE B0 Event Source Select 15 1 read-write IN_MODE A0 Event Source Select 4 2 read-write OUT_MODE A0 Event Source Select 0 2 read-write POLSEL B0 Event Source Select 2 2 read-write DBFED Falling Edge Dead Zorn Delay Setting Register 0x44 32 read-write n 0x0 0xFFFFFFFF DBRED Rising Edge Dead Zorn Delay Setting Register 0x40 32 read-write n 0x0 0xFFFFFFFF ETCLR Event trigger clear 0x70 32 read-write n 0x0 0xFFFFFFFF INT A0 Event Source Select 0 1 read-write SOCA B0 Event Source Select 2 1 read-write SOCB A0 Event Source Select 3 1 read-write ETFLG Event trigger flags 0x6C 32 read-write n 0x0 0xFFFFFFFF CTRDIR B0 Event Source Select 31 1 read-only INT A0 Event Source Select 0 1 read-only SOCA B0 Event Source Select 2 1 read-only SOCB A0 Event Source Select 3 1 read-only ETFRC Event trigger force 0x74 32 read-write n 0x0 0xFFFFFFFF INT A0 Event Source Select 0 1 read-write SOCA B0 Event Source Select 2 1 read-write SOCB A0 Event Source Select 3 1 read-write ETPS Event trigger pre-scaler 0x68 32 read-write n 0x0 0xFFFFFFFF INTCNT B0 Event Source Select 2 2 read-only INTPRD A0 Event Source Select 0 2 read-write SOCACNT B0 Event Source Select 10 2 read-only SOCAPRD A0 Event Source Select 8 2 read-write SOCBCNT B0 Event Source Select 14 2 read-only SOCBPRD A0 Event Source Select 12 2 read-write ETSEL Event trigger selection 0x64 32 read-write n 0x0 0xFFFFFFFF INTEN B0 Event Source Select 3 1 read-write INTESEL A0 Event Source Select 0 3 read-write SOCAEN B0 Event Source Select 11 1 read-write SOCASEL A0 Event Source Select 8 3 read-write SOCBEN B0 Event Source Select 15 1 read-write SOCBSEL A0 Event Source Select 12 3 read-write TBCTL Time Reference Control Register 0x0 32 read-write n 0x0 0xFFFFFFFF CLKDIV A3 Event Source Select 10 3 read-write CTRMODE Time Reference Status Register 0 2 read-write FREE_SOFT B3 Event Source Select 14 2 read-write HSPCLKDIV B2 Event Source Select 7 3 read-write PHSDIR B3 Event Source Select 13 1 read-write PHSEN Time Reference Phase Register 2 1 read-write PRDLD Time Reference Counter Register 3 1 read-write SWFSYNC A2 Event Source Select 6 1 read-write SYNCOSEL B1 Event Source Select 4 2 read-write TBCTR Time Reference Counter Register 0x10 32 read-write n 0x0 0xFFFFFFFF TBPHS Time Reference Phase Register 0xC 32 read-write n 0x0 0xFFFFFFFF TBPRD Time Reference Period Register 0x14 32 read-write n 0x0 0xFFFFFFFF TBPRDM Time Base Period register Mirror 0xAC 32 read-write n 0x0 0xFFFFFFFF TBSTS Time Reference Status Register 0x4 32 read-write n 0x1 0xFFFFFFFF CTRDIR A0 Event Source Select 0 1 read-write CTRMAX A1 Event Source Select 2 1 read-write SYNCI B0 Event Source Select 1 1 read-write TZCLR Trip zone clear 0x5C 32 read-write n 0x0 0xFFFFFFFF CBC A0 Event Source Select 1 1 read-write INT A0 Event Source Select 0 1 read-write OST B0 Event Source Select 2 1 read-write TZCTL Trip zone control 0x50 32 read-write n 0x0 0xFFFFFFFF SYNC_OUTEN A0 Event Source Select 31 1 read-write TZA A0 Event Source Select 0 2 read-write TZB B0 Event Source Select 2 2 read-write TZEINT Trip zone interrupt enable 0x54 32 read-write n 0x0 0xFFFFFFFF CBC A0 Event Source Select 1 1 read-write OST B0 Event Source Select 2 1 read-write TZFLG Trip zone interrupt flags 0x58 32 read-only n 0x0 0xFFFFFFFF CBC A0 Event Source Select 1 1 read-only INT A0 Event Source Select 0 1 read-only OST B0 Event Source Select 2 1 read-only TZFRC Trip zone force interrupt 0x60 32 read-write n 0x0 0xFFFFFFFF CBC A0 Event Source Select 1 1 read-write OST B0 Event Source Select 2 1 read-write TZSEL Trip zone select 0x48 32 read-write n 0x0 0xFFFFFFFF CBC0 A0 Event Source Select 0 1 read-write CBC1 B0 Event Source Select 1 1 read-write CBC2 A0 Event Source Select 2 1 read-write CBC3 B0 Event Source Select 3 1 read-write CBC4 A0 Event Source Select 4 1 read-write CBC5 B0 Event Source Select 5 1 read-write OSHT0 A0 Event Source Select 8 1 read-write OSHT1 B0 Event Source Select 9 1 read-write OSHT2 A0 Event Source Select 10 1 read-write OSHT3 B0 Event Source Select 11 1 read-write OSHT4 A0 Event Source Select 12 1 read-write OSHT5 B0 Event Source Select 13 1 read-write SPI0 SPI0 module SPI 0x40098000 0x0 0x1000 registers n SPI0 SPI0 Interrupt 3 SSPCPSR Clock prescale Register 0x10 32 read-write n 0x0 0xFFFFFFFF CPSDVSR Clock prescale divisor 0 8 read-write SSPCR0 Control Register 0 0x0 32 read-write n 0x0 0xFFFFFFFF DSS Data Size Select 0 4 read-write FRF Frame format 4 2 read-write SCR Serial Clock rate 8 8 read-write SPH SSPCLKOUT phase 7 1 read-write SPO SSPCLKOUT polarity 6 1 read-write SSPCR1 Control Register 1 0x4 32 read-write n 0x0 0xFFFFFFFF DMALEV DMA RX FIFO trig level 4 3 read-write LBM Loop back mode 0 1 read-write MS Master or Slave mode select 2 1 read-write SOD Clear Data Overrun 3 1 read-write SSE Synchronous serial port enable 1 1 read-write SSPDMACR DMA Control Register 0x24 32 read-write n 0x0 0xFFFFFFFF RXDMAE Receive DMA Enable. 0 1 read-write TXDMAE Transmit DMA Enable 1 1 read-write SSPDR Data Register 0x8 32 read-write n 0x0 0xFFFFFFFF DATA Transmit/Receive FIFO 0 16 read-write SSPICR Interrupt Clear Register 0x20 32 write-only n 0x0 0xFFFFFFFF RORIC Clears the SSPRORINTR interrupt 0 1 write-only RTIC Clears the SSPRTINTR interrupt 1 1 write-only SSPIMSC Interrupt Set or Clear Register 0x14 32 read-write n 0x0 0xFFFFFFFF RORIM Receive overrun interrupt mask 0 1 read-write RTIM Receive timeout interrupt mask 1 1 read-write RXIM Receive FIFO interrupt mask 2 1 read-write TXIM Receive FIFO interrupt mask 3 1 read-write SSPMIS Masked Interrupt Staus Register 0x1C 32 read-only n 0x0 0xFFFFFFFF RORMIS Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt 0 1 read-only RTMIS Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt 1 1 read-only RXMIS Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt 2 1 read-only TXMIS Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt 3 1 read-only SSPPCID0 PrimCell Identification Register0 0xFF0 32 read-only n 0x0 0xFFFFFFFF SSPPCID1 PrimCell Identification Register1 0xFF4 32 read-only n 0x0 0xFFFFFFFF SSPPCID2 PrimCell Identification Register2 0xFF8 32 read-only n 0x0 0xFFFFFFFF SSPPCID3 PrimCell Identification Register3 0xFFC 32 read-only n 0x0 0xFFFFFFFF SSPPID0 Peripheral Identification Register0 0xFE0 32 read-only n 0x0 0xFFFFFFFF SSPPID1 Peripheral Identification Register1 0xFE4 32 read-only n 0x0 0xFFFFFFFF SSPPID2 Peripheral Identification Register2 0xFE8 32 read-only n 0x0 0xFFFFFFFF SSPPID3 Peripheral Identification Register3 0xFEC 32 read-only n 0x0 0xFFFFFFFF SSPRIS Raw Interrupt Status Register 0x18 32 read-only n 0x0 0xFFFFFFFF RORRIS Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt 0 1 read-only RTRIS Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt 1 1 read-only RXRIS Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt 2 1 read-only TXRIS Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt 3 1 read-only SSPSR Status Register 0xC 32 read-only n 0x0 0xFFFFFFFF BSY PrimeCell SSP busy flag 4 1 read-only RFF Receive FIFO full 3 1 read-only RNE Receive FIFO not empty 2 1 read-only TFE Transmit FIFO emptyt 0 1 read-only TNF Transmit FIFO full 1 1 read-only SYSREG SYSREG SYSREG 0x40080000 0x0 0xD00 registers n ACCESS_EN ACCESS ENABLE Register 0x800 32 read-write n 0x0 0xFFFFFFFF CHIP_ID CHIP_ID Register 0x124 32 read-only n 0x0 0xFFFFFFFF ETIMER_CFG ETIMER confige Register 0x14 32 read-write n 0x0 0xFFFFFFFF MISC_CTRL MISC control Register 0xC 32 read-write n 0x0 0xFFFFFFFF PWM_CFG PWM confige Register 0x10 32 read-write n 0x0 0xFFFFFFFF RXEV_CTRL RXEV control Register 0x8 32 read-write n 0x0 0xFFFFFFFF SYSINT_STATUS SYSINT status Register 0x100 32 read-only n 0x0 0xFFFFFFFF cordic_intr cordic_intr 10 1 read-only div_intr div_intr 8 1 read-only eflash_intr eflash_intr 1 1 read-only mac_intr mac_intr 9 1 read-only ppu_intr ppu_intr 0 1 read-only pwm0tz_intr pwm0tz_intr 24 1 read-only pwm0_intr pwm0_intr 16 1 read-only pwm1tz_intr pwm1tz_intr 25 1 read-only pwm1_intr pwm1_intr 17 1 read-only pwm2tz_intr pwm2tz_intr 26 1 read-only pwm2_intr pwm2_intr 18 1 read-only pwm4tz_intr pwm4tz_intr 28 1 read-only pwm4_intr pwm4_intr 20 1 read-only sysram0 sysram0 3 1 read-only sysram0_intr sysram0_intr 2 1 read-only sysram1 sysram1 5 1 read-only sysram1_intr sysram1_intr 4 1 read-only SYSRAM_CTRL RAM control Register 0x4 32 read-write n 0x0 0xFFFFFFFF sysram0_ms sysram0_ms 16 4 read-write sysram0_mse sysram0_mse 23 1 read-write sysram0_parity_err_clr sysram0_parity_err_clr 9 1 read-write sysram0_parity_intren sysram0_parity_intren 8 1 read-write sysram1_ms sysram1_ms 24 4 read-write sysram1_mse sysram1_mse 31 1 read-write sysram1_parity_err_clr sysram1_parity_err_clr 11 1 read-write sysram1_parity_intren sysram1_parity_intren 10 1 read-write SYSRAM_STATUS SYSRAM status Register 0x11C 32 read-only n 0x0 0xFFFFFFFF SYSTICK_CFG SYSTICK confige Register 0x18 32 read-write n 0x0 0xFFFFFFFF VERSION VERSION Register 0xC00 32 read-only n 0x0 0xFFFFFFFF TIM6 TIM6 TIM6 0x400aF000 0x0 0x50 registers n TIM6_T0 TIM6_T0 Interrupt 8 TIM6_T1 TIM6_T1 Interrupt 9 COMPARE0 TIMER0 Compare Counter Register 0x4 32 read-write n 0x0 0xFFFFFFFF COMPARE1 TIMER1 Compare Counter Register 0x14 32 read-write n 0x0 0xFFFFFFFF COUNT0 TIMER0 COUNTER Register 0x0 32 read-write n 0x0 0xFFFFFFFF COUNT1 TIMER1 COUNTER Register 0x10 32 read-write n 0x0 0xFFFFFFFF CTC0 TIMER0 Control Register 0x8 32 read-write n 0xFFFFFFFF 0x0 COUNT0INT_EN COUNT0INT_EN 2 1 read-write COUNTEN COUNTEN 0 1 read-write COUNTFW COUNTFW 1 1 read-write Freerun Freerun 3 1 read-write CTC1 TIMER1 Control Register 0x18 32 read-write n 0xFFFFFFFF 0x0 COUNT0INT_EN COUNT0INT_EN 2 1 read-write COUNTEN COUNTEN 0 1 read-write COUNTFW COUNTFW 1 1 read-write Freerun Freerun 3 1 read-write CTCSEL0 CTCSEL0 0xC 32 read-write n 0x0 0xFFFFFFFF CTCSEL1 CTCSEL1 0x1C 32 read-write n 0x0 0xFFFFFFFF TIMER0 TIMER0 TIMER 0x400AC000 0x0 0x1000 registers n TIMER0 TIMER0 Interrupt 6 TIM_ARR TIM1_ARR register 0x2C 32 read-write n 0x0 0xFFFFFFFF TIM_BDTR TIM1_BDTR Register 0x44 32 read-write n 0x0 0xFFFFFFFF AOE Automatic output enable 14 1 read-write BKE Break enable 12 1 read-write BKP Break polarity 13 1 read-write DTG Dead-time generator setup 0 8 read-write MOE Main output enable 15 1 read-write OSSI OSSI 10 1 read-write OSSR OSSR 11 1 read-write TIM_CCER Time catch/compare enable Register 0x20 32 read-write n 0x0 0xFFFFFFFF CC1E CC1E 0 1 read-write CC1NE CC1NE 2 1 read-write CC1NP CC1NP 3 1 read-write CC1P CC1P 1 1 read-write CC2E CC2E 4 1 read-write CC2NE CC2NE 6 1 read-write CC2NP CC2NP 7 1 read-write CC2P CC2P 5 1 read-write CC3E CC3E 8 1 read-write CC3NE CC3NE 10 1 read-write CC3NP CC3NP 11 1 read-write CC3P CC3P 9 1 read-write CC4E CC4E 12 1 read-write CC4P CC4P 13 1 read-write TIM_CCMR1 TIME Catch/compare mode register 0x18 32 read-write n 0x0 0xFFFFFFFF CC1S Output compare mode CC1S 0 2 read-write CC2S Output compare mode CC2S 8 2 read-write OC1CE Output compare mode OC1CE 7 1 read-write OC1FE Output compare mode OC1FE 2 1 read-write OC1M Output compare mode OC1M 4 3 read-write OC1PE Output compare mode OC1PE 3 1 read-write OC2CE Output compare mode OC2CE 15 1 read-write OC2FE Output compare mode OC2FE 10 1 read-write OC2M Output compare mode OC2M 12 3 read-write OC2PE Output compare mode OC2PE 11 1 read-write TIM_CCMR1_CAP Input capture mode TIME Catch/compare mode register TIM_CCMR1 0x18 32 read-write n 0x0 0xFFFFFFFF CC1S input capture mode CC1S 0 2 read-write CC2S input capture mode CC2S 8 2 read-write IC1F input capture mode IC1F 4 4 read-write IC1PSC input capture mode IC1PSC 2 2 read-write IC2F input capture mode IC2F 12 4 read-write IC2PSC input capture mode IC2PSC 10 2 read-write TIM_CCMR2 TIME Catch/compare mode register 0x1C 32 read-write n 0x0 0xFFFFFFFF CC3S Output compare mode CC3S 0 2 read-write CC4S Output compare mode CC4S 8 2 read-write OC3CE Output compare mode OC3CE 7 1 read-write OC3FE Output compare mode OC3FE 2 1 read-write OC3M Output compare mode OC3M 4 3 read-write OC3PE Output compare mode OC3PE 3 1 read-write OC4CE Output compare mode OC4CE 15 1 read-write OC4FE Output compare mode OC4FE 10 1 read-write OC4M Output compare mode OC4M 12 3 read-write OC4PE Output compare mode OC4PE 11 1 read-write TIM_CCMR2_CAP Input capture mode TIME Catch/compare mode register TIM_CCMR2 0x1C 32 read-write n 0x0 0xFFFFFFFF CC3S input capture mode CC3S 0 2 read-write CC4S input capture mode CC4S 8 2 read-write IC3F input capture mode IC3F 4 4 read-write IC3PSC input capture mode IC3PSC 2 2 read-write IC4F input capture mode IC4F 12 4 read-write IC4PSC input capture mode IC4PSC 10 2 read-write TIM_CCR1 TIM1_CCR1 register 0x34 32 read-write n 0x0 0xFFFFFFFF TIM_CCR2 TIM1_CCR2 register 0x38 32 read-write n 0x0 0xFFFFFFFF TIM_CCR3 TIM1_CCR3 register 0x3C 32 read-write n 0x0 0xFFFFFFFF TIM_CCR4 TIM1_CCR4 register 0x40 32 read-write n 0x0 0xFFFFFFFF TIM_CNT TIMe_CNT register 0x24 32 read-only n 0x0 0xFFFFFFFF TIM_CR1 Time Control Register 0x0 32 read-write n 0x0 0xFFFFFFFF ARPE Auto-reload preload enable 7 1 read-write CEN Counter enable 0 1 read-write CKD Clock division 8 2 read-write CMS Center-aligned mode selection 5 2 read-write DIR counter Direction 4 1 read-write OPM One pulse mode 3 1 read-write UDIS Update disable 1 1 read-write URS Update request source 2 1 read-write TIM_CR2 Time control2 Register 0x4 32 read-write n 0x1 0xFFFFFFFF CCPC catch/compare preloaded control 0 1 read-write CCUS catch/compare control update selection 2 1 read-write MMS Master mode selection 4 2 read-write OIS1 Output Idle state 1 8 1 read-write OIS1N Output Idle state 1 9 1 read-write OIS2 Output Idle state 2 10 1 read-write OIS2N Output Idle state 2 11 1 read-write OIS3 Output Idle state 3 12 1 read-write OIS3N Output Idle state 3 13 1 read-write OIS4 Output Idle state 4 14 1 read-write TI1S TI1 selection 7 1 read-write TIM_DIER Time int enable Register 0xC 32 read-write n 0x0 0xFFFFFFFF BIE BIE 7 1 read-write CC1IE CC1IE 1 1 read-write CC2IE CC2IE 2 1 read-write CC3IE CC3IE 3 1 read-write CC4IE CC4IE 4 1 read-write COMIE COMIE 5 1 read-write TIE TIE 6 1 read-write UIE UIE 0 1 read-write TIM_DTG1 TIM1_DTG1 0x48 32 read-write n 0x0 0xFFFFFFFF TIM_EGR Time event generate Register 0x14 32 read-write n 0x0 0xFFFFFFFF BG Break generation 7 1 read-write CC1G Capture/Compare 1 generation 1 1 read-write CC2G Capture/Compare 2 generation 2 1 read-write CC3G Capture/Compare 3 generation 3 1 read-write CC4G Capture/Compare 4 generation 4 1 read-write COMG Capture/Compare control update generation 5 1 read-write TG Trigger generation 6 1 read-write UG Update generation 0 1 read-write TIM_ISR TIM1_ISR 0x4C 32 read-write n 0x0 0xFFFFFFFF Brk_sel Brk_sel 10 2 read-write Ch1_sel Ch1_sel 2 2 read-write Ch2_sel Ch2_sel 4 2 read-write Ch3_sel Ch3_sel 6 2 read-write Ch4_sel Ch4_sel 8 2 read-write Debug_mode Debug_mode 0 2 read-write Trc_sel Trc_sel 12 2 read-write TIM_PSC TIM1_PSC register 0x28 32 read-write n 0x0 0xFFFFFFFF TIM_RCR TIM1_RCR register 0x30 32 read-write n 0x0 0xFFFFFFFF TIM_SMCR Time slave mode control Register 0x8 32 read-write n 0x0 0xFFFFFFFF ECE External clock enable 14 1 read-write ETF External trigger filter 8 3 read-write ETP External trigger polarity 15 1 read-write ETPS External trigger prescaler 12 2 read-write SMS Slave mode selection 0 3 read-write TS Trigger selection 4 3 read-write TIM_SR TIME status register 0x10 32 read-write n 0x0 0xFFFFFFFF BIF Break interrupt flag 7 1 read-write CC1IF Capture/Compare 1 interrupt flag 1 1 read-write CC1OF Capture/Compare 1 overcapture flag 9 1 read-write CC2IF Capture/Compare 2 interrupt flag 2 1 read-write CC2OF Capture/Compare 2 overcapture flag 10 1 read-write CC3IF Capture/Compare 3 interrupt flag 3 1 read-write CC3OF Capture/Compare 3 overcapture flag 11 1 read-write CC4IF Capture/Compare 4 interrupt flag 4 1 read-write CC4OF Capture/Compare 4 overcapture flag 12 1 read-write COMIF COM interrupt flag 5 1 read-write TIF Trigger interrupt flag 6 1 read-write UIF Update interrupt flag 0 1 read-write UART0 UART0 UART 0x40090000 0x0 0x4C registers n UART0 UART0 Interrupt 0 UARTCR UART0 Control Register 0x30 32 read-write n 0x0 0xFFFFFFFF CTSEn Clear to Send hardware flow control enable 15 1 read-write DTS Data Transmit Ready 10 1 read-write LBE Loopback Enable 7 1 read-write Out1 Out1 12 1 read-write Out2 Out2 13 1 read-write RTS Request to Send 11 1 read-write RTSEn Ready to Send hardware flow control enable 14 1 read-write RXE Receive Enable 9 1 read-write SIREN SIR ENDEC Enable 1 1 read-write SIRLP SIR low-power IrDA mode 2 1 read-write TXE Transmit Enable 8 1 read-write UARTEN UART Enable 0 1 read-write UARTDMACR UART0 DMA Control Register 0x48 32 read-write n 0x0 0xFFFFFFFF DMA_error nUARTDCD Modem Interrupt mask 2 1 read-write RxFIFO_en nUARTRI Modem Interrupt mask 0 1 read-write TxFIFO_en nUARTCTS Modem Interrupt mask 1 1 read-write UARTDR uart data buff 0x0 32 read-write n 0x0 0xFFFFFFFF Break_Error DMA Transmit Size 10 1 read-write DATA UART0 Send And Recive Data 0 8 read-write Framing_Error DMA Transmit Size 8 1 read-write Overrun_Error DMA Transmit Size 11 1 read-write Parity_Error DMA Transmit Size 9 1 read-write UARTFBRD uart board rate mod 0..5 is usefull 0x28 32 read-write n 0x0 0xFFFFFFFF UARTFR UART0 Flag Register 0x18 32 read-only n 0x0 0xFFFFFFFF BUSY Indicate Is Busy 3 1 read-only CTS Clear to Send 0 1 read-only DCD Data Carrier Detect 2 1 read-only DSR Data Set Ready 1 1 read-only RI Ring indicator 8 1 read-only RXFE Receive FIFO Empty 4 1 read-only RXFF Receive FIFO Full 6 1 read-only TXFE Transmit FIFO Empty 7 1 read-only TXFF Transmit FIFO Full 5 1 read-only UARTIBRD uart board rate 0..15 is usefull 0x24 32 read-write n 0x0 0xFFFFFFFF UARTICR UART0 Int Clear Register 0x44 32 write-only n 0x0 0xFFFFFFFF C_BE_IM Clear Break Error Interrupt Mask 9 1 write-only C_FE_IM Clear Framing Error Interrupt Mask 7 1 write-only C_nUARTCTS_IM Clear nUARTCTS Modem Interrupt mask 1 1 write-only C_nUARTDCD_IM Clear nUARTDCD Modem Interrupt mask 2 1 write-only C_nUARTDSR_IM Clear nUARTDSR Modem Interrupt mask 3 1 write-only C_nUARTRI_IM Clear nUARTRI Modem Interrupt mask 0 1 write-only C_OE_IM Clear Overrun Error Interrupt Mask 10 1 write-only C_PF_IM Clear Parity Error Interrupt Mask 8 1 write-only C_Receive_IM Clear Receive Interrupt Mask 4 1 write-only C_RT_IM Clear Receive Ttimeout Interrupt Mask 6 1 write-only C_Transmit_IM Clear Transmit Interrupt Mask 5 1 write-only UARTIFLS fifo int level select 0x34 32 read-write n 0x12 0xFFFFFFFF RXIFLSEL Receive Interrupt FIFO Level Select 3 3 read-write TXIFLSEL Transmit Interrupt FIFO Level Select 0 3 read-write UARTIMSC int enable bit 0x38 32 read-write n 0x0 0xFFFFFFFF BE_IM Break Error Interrupt Mask 9 1 read-write FE_IM Framing Error Interrupt Mask 7 1 read-write nUARTCTS_IM nUARTCTS Modem Interrupt mask 1 1 read-write nUARTDCD_IM nUARTDCD Modem Interrupt mask 2 1 read-write nUARTDSR_IM nUARTDSR Modem Interrupt mask 3 1 read-write nUARTRI_IM nUARTRI Modem Interrupt mask 0 1 read-write OE_IM Overrun Error Interrupt Mask 10 1 read-write PF_IM Parity Error Interrupt Mask 8 1 read-write Receive_IM Receive Interrupt Mask 4 1 read-write RT_IM Receive Ttimeout Interrupt Mask 6 1 read-write Transmit_IM Transmit Interrupt Mask 5 1 read-write UARTLCR_H Line Control 0x2C 32 read-write n 0x0 0xFFFFFFFF EPS Even Parity Select 2 1 read-write FEN FIFO Enable 4 1 read-write PE Parity Enable 1 1 read-write SB Send Break 0 1 read-write SPS Stick Parity Select 7 1 read-write STP2 2 Stop Bits 3 1 read-write WLEN Word Length 5 2 read-write UARTMIS UART0 MASK Interrupt 0x40 32 read-only n 0x0 0xFFFFFFFF BE_MI Break Error Masked Interrupt 9 1 read-only FE_MI Framing Error Masked Interrupt 7 1 read-only nUARTCTS_MI nUARTCTS Modem Masked Interrupt 1 1 read-only nUARTDCD_MI nUARTDCD Modem Masked Interrupt 2 1 read-only nUARTDSR_MI nUARTDSR Modem Masked Interrupt 3 1 read-only nUARTRI_MI nUARTRI Modem Masked Interrupt 0 1 read-only OE_MI Overrun Error Masked Interrupt 10 1 read-only PF_MI Parity Error Masked Interrupt 8 1 read-only Receive_MI Receive Masked Interrupt 4 1 read-only RT_MI Receive Ttimeout Masked Interrupt 6 1 read-only Transmit_MI Transmit Masked Interrupt 5 1 read-only UARTRIS UART0 Int Rigio 0x3C 32 read-only n 0x0 0xFFFFFFFF BE_I Break Error Interrupt 9 1 read-only FE_I Framing Error Interrupt 7 1 read-only nUARTCTS_I nUARTCTS Modem Interrupt 1 1 read-only nUARTDCD_I nUARTDCD Modem Interrupt 2 1 read-only nUARTDSR_I nUARTDSR Modem Interrupt 3 1 read-only nUARTRI_I nUARTRI Modem Interrupt 0 1 read-only OE_I Overrun Error Interrupt 10 1 read-only PF_I Parity Error Interrupt 8 1 read-only Receive_I Receive Interrupt 4 1 read-only RT_I Receive Ttimeout Interrupt 6 1 read-only Transmit_I Transmit Interrupt 5 1 read-only UARTRSR uart rx status 0x4 32 read-write n 0x0 0xFFFFFFFF Break_Error DMA Transmit Size 2 1 read-write Framing_Error DMA Transmit Size 0 1 read-write Overrun_Error DMA Transmit Size 3 1 read-write Parity_Error DMA Transmit Size 1 1 read-write UART1 UART0 UART 0x40091000 0x0 0x4C registers n UART1 Uart1 Interrupt 1 UARTCR UART0 Control Register 0x30 32 read-write n 0x0 0xFFFFFFFF CTSEn Clear to Send hardware flow control enable 15 1 read-write DTS Data Transmit Ready 10 1 read-write LBE Loopback Enable 7 1 read-write Out1 Out1 12 1 read-write Out2 Out2 13 1 read-write RTS Request to Send 11 1 read-write RTSEn Ready to Send hardware flow control enable 14 1 read-write RXE Receive Enable 9 1 read-write SIREN SIR ENDEC Enable 1 1 read-write SIRLP SIR low-power IrDA mode 2 1 read-write TXE Transmit Enable 8 1 read-write UARTEN UART Enable 0 1 read-write UARTDMACR UART0 DMA Control Register 0x48 32 read-write n 0x0 0xFFFFFFFF DMA_error nUARTDCD Modem Interrupt mask 2 1 read-write RxFIFO_en nUARTRI Modem Interrupt mask 0 1 read-write TxFIFO_en nUARTCTS Modem Interrupt mask 1 1 read-write UARTDR uart data buff 0x0 32 read-write n 0x0 0xFFFFFFFF Break_Error DMA Transmit Size 10 1 read-write DATA UART0 Send And Recive Data 0 8 read-write Framing_Error DMA Transmit Size 8 1 read-write Overrun_Error DMA Transmit Size 11 1 read-write Parity_Error DMA Transmit Size 9 1 read-write UARTFBRD uart board rate mod 0..5 is usefull 0x28 32 read-write n 0x0 0xFFFFFFFF UARTFR UART0 Flag Register 0x18 32 read-only n 0x0 0xFFFFFFFF BUSY Indicate Is Busy 3 1 read-only CTS Clear to Send 0 1 read-only DCD Data Carrier Detect 2 1 read-only DSR Data Set Ready 1 1 read-only RI Ring indicator 8 1 read-only RXFE Receive FIFO Empty 4 1 read-only RXFF Receive FIFO Full 6 1 read-only TXFE Transmit FIFO Empty 7 1 read-only TXFF Transmit FIFO Full 5 1 read-only UARTIBRD uart board rate 0..15 is usefull 0x24 32 read-write n 0x0 0xFFFFFFFF UARTICR UART0 Int Clear Register 0x44 32 write-only n 0x0 0xFFFFFFFF C_BE_IM Clear Break Error Interrupt Mask 9 1 write-only C_FE_IM Clear Framing Error Interrupt Mask 7 1 write-only C_nUARTCTS_IM Clear nUARTCTS Modem Interrupt mask 1 1 write-only C_nUARTDCD_IM Clear nUARTDCD Modem Interrupt mask 2 1 write-only C_nUARTDSR_IM Clear nUARTDSR Modem Interrupt mask 3 1 write-only C_nUARTRI_IM Clear nUARTRI Modem Interrupt mask 0 1 write-only C_OE_IM Clear Overrun Error Interrupt Mask 10 1 write-only C_PF_IM Clear Parity Error Interrupt Mask 8 1 write-only C_Receive_IM Clear Receive Interrupt Mask 4 1 write-only C_RT_IM Clear Receive Ttimeout Interrupt Mask 6 1 write-only C_Transmit_IM Clear Transmit Interrupt Mask 5 1 write-only UARTIFLS fifo int level select 0x34 32 read-write n 0x12 0xFFFFFFFF RXIFLSEL Receive Interrupt FIFO Level Select 3 3 read-write TXIFLSEL Transmit Interrupt FIFO Level Select 0 3 read-write UARTIMSC int enable bit 0x38 32 read-write n 0x0 0xFFFFFFFF BE_IM Break Error Interrupt Mask 9 1 read-write FE_IM Framing Error Interrupt Mask 7 1 read-write nUARTCTS_IM nUARTCTS Modem Interrupt mask 1 1 read-write nUARTDCD_IM nUARTDCD Modem Interrupt mask 2 1 read-write nUARTDSR_IM nUARTDSR Modem Interrupt mask 3 1 read-write nUARTRI_IM nUARTRI Modem Interrupt mask 0 1 read-write OE_IM Overrun Error Interrupt Mask 10 1 read-write PF_IM Parity Error Interrupt Mask 8 1 read-write Receive_IM Receive Interrupt Mask 4 1 read-write RT_IM Receive Ttimeout Interrupt Mask 6 1 read-write Transmit_IM Transmit Interrupt Mask 5 1 read-write UARTLCR_H Line Control 0x2C 32 read-write n 0x0 0xFFFFFFFF EPS Even Parity Select 2 1 read-write FEN FIFO Enable 4 1 read-write PE Parity Enable 1 1 read-write SB Send Break 0 1 read-write SPS Stick Parity Select 7 1 read-write STP2 2 Stop Bits 3 1 read-write WLEN Word Length 5 2 read-write UARTMIS UART0 MASK Interrupt 0x40 32 read-only n 0x0 0xFFFFFFFF BE_MI Break Error Masked Interrupt 9 1 read-only FE_MI Framing Error Masked Interrupt 7 1 read-only nUARTCTS_MI nUARTCTS Modem Masked Interrupt 1 1 read-only nUARTDCD_MI nUARTDCD Modem Masked Interrupt 2 1 read-only nUARTDSR_MI nUARTDSR Modem Masked Interrupt 3 1 read-only nUARTRI_MI nUARTRI Modem Masked Interrupt 0 1 read-only OE_MI Overrun Error Masked Interrupt 10 1 read-only PF_MI Parity Error Masked Interrupt 8 1 read-only Receive_MI Receive Masked Interrupt 4 1 read-only RT_MI Receive Ttimeout Masked Interrupt 6 1 read-only Transmit_MI Transmit Masked Interrupt 5 1 read-only UARTRIS UART0 Int Rigio 0x3C 32 read-only n 0x0 0xFFFFFFFF BE_I Break Error Interrupt 9 1 read-only FE_I Framing Error Interrupt 7 1 read-only nUARTCTS_I nUARTCTS Modem Interrupt 1 1 read-only nUARTDCD_I nUARTDCD Modem Interrupt 2 1 read-only nUARTDSR_I nUARTDSR Modem Interrupt 3 1 read-only nUARTRI_I nUARTRI Modem Interrupt 0 1 read-only OE_I Overrun Error Interrupt 10 1 read-only PF_I Parity Error Interrupt 8 1 read-only Receive_I Receive Interrupt 4 1 read-only RT_I Receive Ttimeout Interrupt 6 1 read-only Transmit_I Transmit Interrupt 5 1 read-only UARTRSR uart rx status 0x4 32 read-write n 0x0 0xFFFFFFFF Break_Error DMA Transmit Size 2 1 read-write Framing_Error DMA Transmit Size 0 1 read-write Overrun_Error DMA Transmit Size 3 1 read-write Parity_Error DMA Transmit Size 1 1 read-write WDT WDT WDT 0x4008C000 0x0 0xC04 registers n WWDT WWDT Interrupt 14 WDOGCONTROL WDT Control Register 0x8 32 read-write n 0x0 0xFFFFFFFF INTEN Interrput Enable Control Bit 0 1 read-write RSTEN RST Enable Control Bit 1 1 read-write WDOGINTCLR WDT Interrput Clear 0xC 32 write-only n 0x0 0xFFFFFFFF WDOGLOAD WDT Reload Register 0x0 32 read-write n 0x0 0xFFFFFFFF WDOGLOCK WDT Locked Register 0xC00 32 read-write n 0x0 0xFFFFFFFF WDOGMIS WDT Mask Interrput 0x14 32 read-only n 0x0 0xFFFFFFFF WDOGMINT WDT Mask Interrput flag Bit 0 1 read-only WDOGRIS WDT Original Interrput 0x10 32 read-only n 0x0 0xFFFFFFFF WDOGINT WDT Original Interrput flag Bit 0 1 read-only WDOGVALUE WDT Current Counter 0x4 32 read-only n 0x0 0xFFFFFFFF