Name | max Clock(MHz) | Flash (kB) | RAM (kB) | Vcc min(V) | Vcc max(V) | operation temperature min(°C) | operation temperature max(°C) | description |
---|---|---|---|---|---|---|---|---|
RP2040 | 133 | 0 | 264 | 1.62 | 3.63 | -40 | 85 | |
RP2350 | Dual Cortex-M33 or Hazard3 processors at 150MHz 520kB on-chip SRAM, in 10 independent banks Extended low-power sleep states with optional SRAM retention: as low as 10uA DVDD 8kB of one-time-programmable storage (OTP) Up to 16MB of external QSPI flash/PSRAM via dedicated QSPI bus Additional 16MB flash/PSRAM accessible via optional second chip-select On-chip switched-mode power supply to generate core voltage Low-quiescent-current LDO mode can be enabled for sleep states 2x on-chip PLLs for internal or external clock generation GPIOs are 5V-tolerant (powered), and 3.3V-failsafe (unpowered) Security features: Optional boot signing, enforced by on-chip mask ROM, with key fingerprint in OTP Protected OTP storage for optional boot decryption key Global bus filtering based on Arm or RISC-V security/privilege levels Peripherals, GPIOs and DMA channels individually assignable to security domains Hardware mitigations for fault injection attacks Hardware SHA-256 accelerator Peripherals: 2x UARTs 2x SPI controllers 2x I2C controllers 24x PWM channels USB 1.1 controller and PHY, with host and device support 12x PIO state machines 1x HSTX peripheral |
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