esp32

Vendor Web: Espressif

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All devices of this Vendor

Name : esp32

Architecture

Architecture : (Xtensa LX6)

revision : 1

endian : little

Floating Point Unit (FPU) : available

Number of relevant bits in Interrupt priority : 3

Peripherals

name : AES
description :
base address : 0x0

name : APB_CTRL
description :
base address : 0x0

name : BB
description :
base address : 0x0

name : BT
description :
base address : 0x0

name : BT_BB
description :
base address : 0x0
Interrupt (4) BT_BB_INTR : interrupt of BT BB, level
Interrupt (5) BT_BB_NMI : interrupt of BT BB, NMI, use if BB have bug to fix in NMI

name : BT_MAC
description :
base address : 0x0
Interrupt (3) BT_MAC_INTR : will be cancelled

name : CAN
description :
base address : 0x0
Interrupt (45) CAN_INTR : interrupt of can, level

name : DPORT
description :
base address : 0x0

name : EFUSE
description :
base address : 0x0
Interrupt (44) EFUSE_INTR : interrupt of efuse, level, not likely to use

name : EMAC
description :
base address : 0x0

name : ETH
description :
base address : 0x0
Interrupt (38) ETH_MAC_INTR : interrupt of ethernet mac, level

name : ETH_MAC
description :
base address : 0x0

name : FE
description :
base address : 0x0

name : FE2
description :
base address : 0x0

name : FRC_TIMER
description :
base address : 0x0

name : GPIO
description :
base address : 0x0
Interrupt (22) GPIO_INTR : interrupt of GPIO, level
Interrupt (23) GPIO_NMI : interrupt of GPIO, NMI

name : GPIO_SD
description :
base address : 0x0

name : HINF
description :
base address : 0x0

name : I2C
description :
base address : 0x0
Interrupt (39) PWM0_INTR : interrupt of PWM0, level, Reserved
Interrupt (40) PWM1_INTR : interrupt of PWM1, level, Reserved
Interrupt (41) PWM2_INTR : interrupt of PWM2, level
Interrupt (42) PWM3_INTR : interrupt of PWM3, level
Interrupt (49) I2C_EXT0_INTR : interrupt of I2C controller0, level
Interrupt (50) I2C_EXT1_INTR : interrupt of I2C controller1, level

name : I2C0
description :
base address : 0x0

name : I2C1
description :
base address : 0x0

name : I2S
description :
base address : 0x0
Interrupt (32) I2S0_INTR : interrupt of I2S0, level
Interrupt (33) I2S1_INTR : interrupt of I2S1, level

name : I2S1
description :
base address : 0x0

name : IO_MUX
description :
base address : 0x0

name : LEDC
description :
base address : 0x0
Interrupt (43) LEDC_INTR : interrupt of LED PWM, level

name : MCPWM
description :
base address : 0x0

name : NRX
description :
base address : 0x0

name : PCNT
description :
base address : 0x0
Interrupt (48) PCNT_INTR : interrupt of pluse count, level

name : PWM0
description :
base address : 0x0

name : PWM1
description :
base address : 0x0

name : PWM2
description :
base address : 0x0

name : PWM3
description :
base address : 0x0

name : RMT
description :
base address : 0x0
Interrupt (47) RMT_INTR : interrupt of remote controller, level

name : RSA
description :
base address : 0x0
Interrupt (51) RSA_INTR : interrupt of RSA accelerator, level

name : RTCCNTL
description :
base address : 0x0
Interrupt (46) RTC_CORE_INTR : interrupt of rtc core, level, include rtc watchdog

name : RTCIO
description :
base address : 0x0

name : RTCMEM0
description :
base address : 0x0

name : RTCMEM1
description :
base address : 0x0

name : RTCMEM2
description :
base address : 0x0

name : RTC_I2C
description :
base address : 0x0

name : RW_BLE
description :
base address : 0x0
Interrupt (7) RWBLE_INTR : interrupt of RWBLE, level
Interrupt (9) RWBLE_NMI : interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI

name : RW_BT
description :
base address : 0x0
Interrupt (6) RWBT_INTR : interrupt of RWBT, level
Interrupt (8) RWBT_NMI : interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI

name : SDIO
description :
base address : 0x0
Interrupt (37) SDIO_HOST_INTR : interrupt of SD/SDIO/MMC HOST, level

name : SDMMC
description :
base address : 0x0

name : SENS
description :
base address : 0x0

name : SHA
description :
base address : 0x0

name : SLC
description :
base address : 0x0
Interrupt (10) SLC0_INTR : interrupt of SLC0, level
Interrupt (11) SLC1_INTR : interrupt of SLC1, level

name : SLCHOST
description :
base address : 0x0

name : SPI
description :
base address : 0x0
Interrupt (52) SPI1_DMA_INTR : interrupt of SPI1 DMA, SPI1 is for flash read/write, do not use this
Interrupt (53) SPI2_DMA_INTR : interrupt of SPI2 DMA, level
Interrupt (54) SPI3_DMA_INTR : interrupt of SPI3 DMA, level

name : SPI0
description :
base address : 0x0

name : SPI1
description :
base address : 0x0

name : SPI2
description :
base address : 0x0

name : SPI3
description :
base address : 0x0

name : SPI_ENCRYPT
description :
base address : 0x0

name : SYSCON
description :
base address : 0x0

name : TIMG
description :
base address : 0x0
Interrupt (14) TG0_T0_LEVEL_INTR : interrupt of TIMER_GROUP0, TIMER0, level, we would like use EDGE for timer if permission
Interrupt (15) TG0_T1_LEVEL_INTR : interrupt of TIMER_GROUP0, TIMER1, level, we would like use EDGE for timer if permission
Interrupt (16) TG0_WDT_LEVEL_INTR : interrupt of TIMER_GROUP0, WATCHDOG, level
Interrupt (17) TG0_LACT_LEVEL_INTR : interrupt of TIMER_GROUP0, LACT, level
Interrupt (18) TG1_T0_LEVEL_INTR : interrupt of TIMER_GROUP1, TIMER0, level, we would like use EDGE for timer if permission
Interrupt (19) TG1_T1_LEVEL_INTR : interrupt of TIMER_GROUP1, TIMER1, level, we would like use EDGE for timer if permission
Interrupt (20) TG1_WDT_LEVEL_INTR : interrupt of TIMER_GROUP1, WATCHDOG, level
Interrupt (21) TG1_LACT_LEVEL_INTR : interrupt of TIMER_GROUP1, LACT, level
Interrupt (58) TG0_T0_EDGE_INTR : interrupt of TIMER_GROUP0, TIMER0, EDGE
Interrupt (59) TG0_T1_EDGE_INTR : interrupt of TIMER_GROUP0, TIMER1, EDGE
Interrupt (60) TG0_WDT_EDGE_INTR : interrupt of TIMER_GROUP0, WATCH DOG, EDGE
Interrupt (61) TG0_LACT_EDGE_INTR : interrupt of TIMER_GROUP0, LACT, EDGE
Interrupt (62) TG1_T0_EDGE_INTR : interrupt of TIMER_GROUP1, TIMER0, EDGE
Interrupt (63) TG1_T1_EDGE_INTR : interrupt of TIMER_GROUP1, TIMER1, EDGE
Interrupt (64) TG1_WDT_EDGE_INTR : interrupt of TIMER_GROUP1, WATCHDOG, EDGE
Interrupt (65) TG1_LACT_EDGE_INTR : interrupt of TIMER_GROUP0, LACT, EDGE

name : TIMG0
description :
base address : 0x0

name : TIMG1
description :
base address : 0x0

name : UART
description :
base address : 0x0
Interrupt (28) SPI0_INTR : interrupt of SPI0, level, SPI0 is for Cache Access, do not use this
Interrupt (29) SPI1_INTR : interrupt of SPI1, level, SPI1 is for flash read/write, do not use this
Interrupt (30) SPI2_INTR : interrupt of SPI2, level
Interrupt (31) SPI3_INTR : interrupt of SPI3, level
Interrupt (34) UART0_INTR : interrupt of UART0, level
Interrupt (35) UART1_INTR : interrupt of UART1, level
Interrupt (36) UART2_INTR : interrupt of UART2, level

name : UART0
description :
base address : 0x0

name : UART1
description :
base address : 0x0

name : UART2
description :
base address : 0x0

name : UHCI
description :
base address : 0x0
Interrupt (12) UHCI0_INTR : interrupt of UHCI0, level
Interrupt (13) UHCI1_INTR : interrupt of UHCI1, level

name : UHCI0
description :
base address : 0x0

name : UHCI1
description :
base address : 0x0

name : WDT
description :
base address : 0x0
Interrupt (55) WDT_INTR : will be cancelled

name : WIFI_BB
description :
base address : 0x0
Interrupt (2) WIFI_BB_INTR : interrupt of WiFi BB, level, we can do some calibration

name : WIFI_MAC
description :
base address : 0x0
Interrupt (0) WIFI_MAC_INTR : interrupt of WiFi MAC, level
Interrupt (1) WIFI_MAC_NMI : interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI

name : XTENSA
description :
base address : 0x0
Interrupt (24) FROM_CPU_INTR0 : interrupt0 generated from a CPU, level
Interrupt (25) FROM_CPU_INTR1 : interrupt1 generated from a CPU, level
Interrupt (26) FROM_CPU_INTR2 : interrupt2 generated from a CPU, level
Interrupt (27) FROM_CPU_INTR3 : interrupt3 generated from a CPU, level
Interrupt (56) TIMER1_INTR : will be cancelled
Interrupt (57) TIMER2_INTR : will be cancelled
Interrupt (66) MMU_IA_INTR : interrupt of MMU Invalid Access, LEVEL
Interrupt (67) MPU_IA_INTR : interrupt of MPU Invalid Access, LEVEL
Interrupt (68) CACHE_IA_INTR : interrupt of Cache Invalid Access, LEVEL

name : XTENSA_INTERNAL
description :
base address : 0x0
Interrupt (69) INTERNAL_TIMER0_INTR : Internal Timer 0 interrupt
Interrupt (70) INTERNAL_SOFTWARE_LEVEL_1_INTR : Software Level 1 interrupt
Interrupt (71) INTERNAL_PROFILING_INTR : Profiling interrupt
Interrupt (72) INTERNAL_TIMER1_INTR : Internal Timer 1 interrupt
Interrupt (73) INTERNAL_TIMER2_INTR : Internal Timer 1 interrupt
Interrupt (74) INTERNAL_SOFTWARE_LEVEL_3_INTR : Software Level 3 interrupt


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